Home
last modified time | relevance | path

Searched refs:HWRITE4 (Results 1 – 25 of 124) sorted by relevance

12345

/openbsd/sys/dev/fdt/
H A Drktcphy.c106 #define HWRITE4(sc, reg, val) \ macro
250 HWRITE4(sc, PMA_CMN_CTRL1, 0x830); in rktcphy_enable()
264 HWRITE4(sc, CMN_PLL0_INTDIV, 0xd0); in rktcphy_enable()
278 HWRITE4(sc, TX_PSC_A0(0), 0x7799); in rktcphy_enable()
279 HWRITE4(sc, TX_PSC_A1(0), 0x7798); in rktcphy_enable()
280 HWRITE4(sc, TX_PSC_A2(0), 0x5098); in rktcphy_enable()
281 HWRITE4(sc, TX_PSC_A3(0), 0x5098); in rktcphy_enable()
285 HWRITE4(sc, RX_PSC_A0(1), 0xa6fd); in rktcphy_enable()
286 HWRITE4(sc, RX_PSC_A1(1), 0xa6fd); in rktcphy_enable()
287 HWRITE4(sc, RX_PSC_A2(1), 0xa410); in rktcphy_enable()
[all …]
H A Dsxirsb.c230 HWRITE4(sc, RSB_CMD, SRTA); in sxirsb_init()
291 HWRITE4(sc, RSB_STAT, stat); in sxirsb_do_trans()
304 HWRITE4(sc, RSB_CMD, RD8); in rsb_read_1()
306 HWRITE4(sc, RSB_AR, addr); in rsb_read_1()
322 HWRITE4(sc, RSB_CMD, RD16); in rsb_read_2()
324 HWRITE4(sc, RSB_AR, addr); in rsb_read_2()
340 HWRITE4(sc, RSB_CMD, WR8); in rsb_write_1()
342 HWRITE4(sc, RSB_AR, addr); in rsb_write_1()
343 HWRITE4(sc, RSB_DATA, data); in rsb_write_1()
357 HWRITE4(sc, RSB_CMD, WR16); in rsb_write_2()
[all …]
H A Damlpciephy.c132 HWRITE4(sc, PHY_R0, reg); in amlpciephy_enable()
149 HWRITE4(sc, PHY_R0, reg); in amlpciephy_enable()
195 HWRITE4(sc, PHY_R4, addr << 2); in amlpciephy_addr()
196 HWRITE4(sc, PHY_R4, addr << 2); in amlpciephy_addr()
207 HWRITE4(sc, PHY_R4, addr << 2); in amlpciephy_addr()
226 HWRITE4(sc, PHY_R4, 0); in amlpciephy_read()
238 HWRITE4(sc, PHY_R4, 0); in amlpciephy_read()
257 HWRITE4(sc, PHY_R4, data << 2); in amlpciephy_write()
258 HWRITE4(sc, PHY_R4, data << 2); in amlpciephy_write()
269 HWRITE4(sc, PHY_R4, data << 2); in amlpciephy_write()
[all …]
H A Drkspi.c171 HWRITE4(sc, SPI_ENR, 0); in rkspi_attach()
172 HWRITE4(sc, SPI_DMACR, 0); in rkspi_attach()
175 HWRITE4(sc, SPI_IPR, 0); in rkspi_attach()
176 HWRITE4(sc, SPI_IMR, 0); in rkspi_attach()
195 HWRITE4(sc, SPI_ENR, 0); in rkspi_detach()
196 HWRITE4(sc, SPI_IMR, 0); in rkspi_detach()
245 HWRITE4(sc, SPI_ENR, 0); in rkspi_config()
246 HWRITE4(sc, SPI_SER, 0); in rkspi_config()
286 HWRITE4(sc, SPI_ENR, 1); in rkspi_transfer()
311 HWRITE4(sc, SPI_ENR, 0); in rkspi_transfer()
[all …]
H A Dmvrng.c50 #define HWRITE4(sc, reg, val) \ macro
53 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
55 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
107 HWRITE4(sc, RNG_CONFIG, 0x5 << RNG_CONFIG_MIN_CYCLES_SHIFT | in mvrng_attach()
109 HWRITE4(sc, RNG_FRODETUNE, 0); in mvrng_attach()
110 HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK); in mvrng_attach()
126 HWRITE4(sc, RNG_ALARMMASK, 0); in mvrng_rnd()
127 HWRITE4(sc, RNG_ALARMSTOP, 0); in mvrng_rnd()
134 HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK); in mvrng_rnd()
135 HWRITE4(sc, RNG_STATUS, RNG_STATUS_SHUTDOWN); in mvrng_rnd()
[all …]
H A Drkgpio.c72 #define HWRITE4(sc, reg, val) \ macro
182 HWRITE4(sc, GPIO_INT_MASK_L, ~0); in rkgpio_attach()
183 HWRITE4(sc, GPIO_INT_MASK_H, ~0); in rkgpio_attach()
184 HWRITE4(sc, GPIO_INT_EN_L, ~0); in rkgpio_attach()
185 HWRITE4(sc, GPIO_INT_EN_H, ~0); in rkgpio_attach()
187 HWRITE4(sc, GPIO_INTMASK, ~0); in rkgpio_attach()
188 HWRITE4(sc, GPIO_INTEN, ~0); in rkgpio_attach()
302 HWRITE4(sc, GPIO_PORT_EOI_L, in rkgpio_intr()
304 HWRITE4(sc, GPIO_PORT_EOI_H, in rkgpio_intr()
307 HWRITE4(sc, GPIO_PORTS_EOI, status); in rkgpio_intr()
[all …]
H A Dimxtmu.c56 #define HWRITE4(sc, reg, val) \ macro
59 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
61 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
140 HWRITE4(sc, TMU_MQ_TIER, 0); in imxtmu_attach()
142 HWRITE4(sc, TMU_MQ_TMR, 0); in imxtmu_attach()
148 HWRITE4(sc, TMU_MQ_TTR0CR, range[0]); in imxtmu_attach()
149 HWRITE4(sc, TMU_MQ_TTR1CR, range[1]); in imxtmu_attach()
150 HWRITE4(sc, TMU_MQ_TTR2CR, range[2]); in imxtmu_attach()
151 HWRITE4(sc, TMU_MQ_TTR3CR, range[3]); in imxtmu_attach()
161 HWRITE4(sc, TMU_MQ_TTCFGR, calibration[i + 0]); in imxtmu_attach()
[all …]
H A Drkcomphy.c101 #define HWRITE4(sc, reg, val) \ macro
104 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
179 HWRITE4(sc, COMBO_PIPE_PHY_REG(32), reg); in rkcomphy_rk3568_pll_tune()
186 HWRITE4(sc, COMBO_PIPE_PHY_REG(5), reg); in rkcomphy_rk3568_pll_tune()
230 HWRITE4(sc, COMBO_PIPE_PHY_REG(31), reg); in rkcomphy_rk3568_enable()
236 HWRITE4(sc, COMBO_PIPE_PHY_REG(14), reg); in rkcomphy_rk3568_enable()
247 HWRITE4(sc, COMBO_PIPE_PHY_REG(6), in rkcomphy_rk3568_enable()
280 HWRITE4(sc, COMBO_PIPE_PHY_REG(14), reg); in rkcomphy_rk3568_enable()
284 HWRITE4(sc, COMBO_PIPE_PHY_REG(15), reg); in rkcomphy_rk3568_enable()
304 HWRITE4(sc, COMBO_PIPE_PHY_REG(31), reg); in rkcomphy_rk3568_enable()
[all …]
H A Damlusbphy.c85 #define HWRITE4(sc, reg, val) \ macro
88 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
90 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
168 HWRITE4(sc, PHY_R16, (20 << PHY_R16_MPLL_M_SHIFT) | in amlusbphy_enable()
172 HWRITE4(sc, PHY_R17, (0 << PHY_R17_MPLL_FRAC_IN_SHIFT) | in amlusbphy_enable()
177 HWRITE4(sc, PHY_R18, (1 << PHY_R18_MPLL_LKW_SEL_SHIFT) | in amlusbphy_enable()
188 HWRITE4(sc, PHY_R16, (20 << PHY_R16_MPLL_M_SHIFT) | in amlusbphy_enable()
201 HWRITE4(sc, PHY_R4, (0xfff << PHY_R4_CALIB_CODE_SHIFT) | in amlusbphy_enable()
206 HWRITE4(sc, PHY_R3, (0 << PHY_R3_SQUELCH_REF_SHIFT) | in amlusbphy_enable()
210 HWRITE4(sc, PHY_R14, 0); in amlusbphy_enable()
[all …]
H A Drktemp.c81 #define HWRITE4(sc, reg, val) \ macro
433 HWRITE4(sc, TSADC_AUTO_CON, auto_con); in rktemp_attach()
437 HWRITE4(sc, TSADC_V3_COMP_SHUT(i), in rktemp_attach()
439 HWRITE4(sc, TSADC_V3_AUTO_SRC, in rktemp_attach()
446 HWRITE4(sc, TSADC_V3_HLT_INT_PD, in rktemp_attach()
461 HWRITE4(sc, TSADC_V3_CRU_EN, cru_en); in rktemp_attach()
467 HWRITE4(sc, TSADC_USER_CON, in rktemp_attach()
481 HWRITE4(sc, TSADC_AUTO_CON, auto_con); in rktemp_attach()
485 HWRITE4(sc, TSADC_COMP_SHUT(i), in rktemp_attach()
503 HWRITE4(sc, TSADC_INT_EN, int_en); in rktemp_attach()
[all …]
H A Damlclock.c108 #define HWRITE4(sc, reg, val) \ macro
263 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
275 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
312 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
321 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
333 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
343 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
352 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
364 HWRITE4(sc, offset, reg); in amlclock_set_cpu_freq()
401 HWRITE4(sc, offset, reg); in amlclock_set_pll_freq()
[all …]
H A Dbcm2835_bsc.c66 #define HWRITE4(sc, reg, val) \ macro
142 HWRITE4(sc, BSC_DIV, div); in bcmbsc_attach()
170 HWRITE4(sc, BSC_S, HREAD4(sc, BSC_S)); in bcmbsc_acquire_bus()
180 HWRITE4(sc, BSC_C, BSC_C_CLEAR); in bcmbsc_release_bus()
227 HWRITE4(sc, BSC_FIFO, buf[i]); in bcmbsc_write()
244 HWRITE4(sc, BSC_A, addr); in bcmbsc_exec()
247 HWRITE4(sc, BSC_DLEN, cmdlen); in bcmbsc_exec()
252 HWRITE4(sc, BSC_C, ctrl); in bcmbsc_exec()
261 HWRITE4(sc, BSC_DLEN, buflen); in bcmbsc_exec()
262 HWRITE4(sc, BSC_C, ctrl | BSC_C_READ); in bcmbsc_exec()
[all …]
H A Ddwmmc.c157 #define HWRITE4(sc, reg, val) \ macro
396 HWRITE4(sc, SDMMC_INTMASK, 0); in dwmmc_attach()
497 HWRITE4(sc, SDMMC_IDINTEN32, in dwmmc_init_descriptors32()
524 HWRITE4(sc, SDMMC_IDINTEN64, in dwmmc_init_descriptors64()
527 HWRITE4(sc, SDMMC_DBADDRH, in dwmmc_init_descriptors64()
659 HWRITE4(sc, SDMMC_CLKENA, 0); in dwmmc_bus_clock()
660 HWRITE4(sc, SDMMC_CLKSRC, 0); in dwmmc_bus_clock()
670 HWRITE4(sc, SDMMC_CLKDIV, div); in dwmmc_bus_clock()
880 HWRITE4(sc, SDMMC_FIFOTH, in dwmmc_fifo_setup()
937 HWRITE4(sc, SDMMC_CARDTHRCTL, in dwmmc_exec_command()
[all …]
H A Dmvkpcie.c129 #define HWRITE4(sc, reg, val) \ macro
383 HWRITE4(sc, PCIE_ERR_CAPCTL, in mvkpcie_attach()
389 HWRITE4(sc, PCIE_DEV_CTRL_STATS, in mvkpcie_attach()
393 HWRITE4(sc, PCIE_CORE_CTRL2, in mvkpcie_attach()
399 HWRITE4(sc, LMI_DEBUG_CTRL, reg); in mvkpcie_attach()
442 HWRITE4(sc, PCIE_LINK_CTRL_STAT, in mvkpcie_attach()
677 HWRITE4(sc, PIO_CTRL, reg); in mvkpcie_conf_read()
679 HWRITE4(sc, PIO_ADDR_MS, 0); in mvkpcie_conf_read()
720 HWRITE4(sc, PIO_CTRL, reg); in mvkpcie_conf_write()
722 HWRITE4(sc, PIO_ADDR_MS, 0); in mvkpcie_conf_write()
[all …]
H A Drkemmcphy.c64 #define HWRITE4(sc, reg, val) \ macro
166 HWRITE4(sc, GRF_EMMCPHY_CON6, GRF_EMMCPHY_CON6_DR_CLR | impedance); in rkemmcphy_enable()
168 HWRITE4(sc, GRF_EMMCPHY_CON0, in rkemmcphy_enable()
170 HWRITE4(sc, GRF_EMMCPHY_CON0, in rkemmcphy_enable()
173 HWRITE4(sc, GRF_EMMCPHY_CON6, in rkemmcphy_enable()
178 HWRITE4(sc, GRF_EMMCPHY_CON6, GRF_EMMCPHY_CON6_PDB_CLR | in rkemmcphy_enable()
190 HWRITE4(sc, GRF_EMMCPHY_CON0, GRF_EMMCPHY_CON0_FREQSEL_CLR | freqsel); in rkemmcphy_enable()
191 HWRITE4(sc, GRF_EMMCPHY_CON6, GRF_EMMCPHY_CON6_ENDLL_CLR | in rkemmcphy_enable()
H A Dexrtc.c43 #define HWRITE4(sc, reg, val) \ macro
137 HWRITE4(sc, RTCSEC, TOBCD(dt.dt_sec)); in exrtc_settime()
138 HWRITE4(sc, RTCMIN, TOBCD(dt.dt_min)); in exrtc_settime()
139 HWRITE4(sc, RTCHOUR, TOBCD(dt.dt_hour)); in exrtc_settime()
140 HWRITE4(sc, RTCDAY, TOBCD(dt.dt_day)); in exrtc_settime()
141 HWRITE4(sc, RTCMON, TOBCD(dt.dt_mon)); in exrtc_settime()
142 HWRITE4(sc, RTCYEAR, TOBCD(dt.dt_year - 1900)); in exrtc_settime()
145 HWRITE4(sc, RTCCTRL, val | RTCCTRL_RTCEN); in exrtc_settime()
/openbsd/sys/arch/armv7/omap/
H A Domrng.c57 #define HWRITE4(sc, reg, val) \ macro
60 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
62 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
117 HWRITE4(sc, RNG_CONFIG, 0x21 << RNG_CONFIG_MIN_CYCLES_SHIFT | in omrng_attach()
119 HWRITE4(sc, RNG_FRODETUNE, 0); in omrng_attach()
120 HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK); in omrng_attach()
139 HWRITE4(sc, RNG_ALARMMASK, 0); in omrng_rnd()
140 HWRITE4(sc, RNG_ALARMSTOP, 0); in omrng_rnd()
147 HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK); in omrng_rnd()
148 HWRITE4(sc, RNG_INTACK, RNG_INTACK_SHUTDOWN); in omrng_rnd()
[all …]
/openbsd/sys/arch/riscv64/dev/
H A Dsxitimer.c48 #define HWRITE4(sc, reg, val) \ macro
109 HWRITE4(sc, TMR_IRQ_EN, 0); in sxitimer_attach()
126 HWRITE4(sc, TMR0_INTV_VALUE, 0); in sxitimer_attach()
127 HWRITE4(sc, TMR0_CTRL, TMR0_MODE_SINGLE | TMR0_CLK_PRES_1 | in sxitimer_attach()
129 HWRITE4(sc, TMR_IRQ_STA, TMR0_IRQ_PEND); in sxitimer_attach()
130 HWRITE4(sc, TMR_IRQ_EN, TMR0_IRQ_EN); in sxitimer_attach()
147 HWRITE4(sc, TMR_IRQ_STA, TMR0_IRQ_PEND); in sxitimer_intr()
164 HWRITE4(sc, TMR0_INTV_VALUE, cycles); in sxitimer_rearm()
165 HWRITE4(sc, TMR0_CTRL, TMR0_MODE_SINGLE | TMR0_CLK_PRES_1 | in sxitimer_rearm()
174 HWRITE4(sc, TMR0_INTV_VALUE, 1); in sxitimer_trigger()
[all …]
H A Dmpfiic.c83 #define HWRITE4(sc, reg, val) \ macro
172 HWRITE4(sc, I2C_CTRL, sc->sc_ctrl); in mpfiic_attach()
173 HWRITE4(sc, I2C_CTRL, 0); in mpfiic_attach()
176 HWRITE4(sc, I2C_SLAVE0ADR, 0); in mpfiic_attach()
177 HWRITE4(sc, I2C_SLAVE1ADR, 0); in mpfiic_attach()
180 HWRITE4(sc, I2C_SMBUS, 0); in mpfiic_attach()
263 HWRITE4(sc, I2C_CTRL, 0); in mpfiic_i2c_send_stop()
291 HWRITE4(sc, I2C_CTRL, sc->sc_ctrl); in mpfiic_i2c_initiate_xfer()
305 HWRITE4(sc, I2C_CTRL, sc->sc_ctrl | ack); in mpfiic_i2c_read_byte()
329 HWRITE4(sc, I2C_DATA, data); in mpfiic_i2c_write_byte()
[all …]
/openbsd/sys/arch/arm64/dev/
H A Dapliic.c58 #define HWRITE4(sc, reg, val) \ macro
61 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
63 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
170 HWRITE4(sc, I2C_SMSTA, reg); in apliic_wait()
174 HWRITE4(sc, I2C_SMSTA, I2C_SMSTA_XEN); in apliic_wait()
201 HWRITE4(sc, I2C_SMSTA, reg); in apliic_exec()
206 HWRITE4(sc, I2C_MTXFIFO, ((uint8_t *)cmd)[i]); in apliic_exec()
207 HWRITE4(sc, I2C_MTXFIFO, ((uint8_t *)cmd)[cmdlen - 1] | in apliic_exec()
216 HWRITE4(sc, I2C_MTXFIFO, I2C_MTXFIFO_READ | buflen | in apliic_exec()
231 HWRITE4(sc, I2C_MTXFIFO, ((uint8_t *)buf)[i]); in apliic_exec()
[all …]
H A Daplspi.c97 #define HWRITE4(sc, reg, val) \ macro
154 HWRITE4(sc, SPI_PIN, SPI_PIN_CS); in aplspi_attach()
184 HWRITE4(sc, SPI_CLKCFG, 0); in aplspi_config()
187 HWRITE4(sc, SPI_CLKIDLE, 0); in aplspi_config()
189 HWRITE4(sc, SPI_CONFIG, SPI_CONFIG_EN); in aplspi_config()
190 HWRITE4(sc, SPI_CLKCFG, SPI_CLKCFG_EN); in aplspi_config()
231 HWRITE4(sc, SPI_TXCNT, len); in aplspi_transfer()
232 HWRITE4(sc, SPI_RXCNT, len); in aplspi_transfer()
252 HWRITE4(sc, SPI_TXDATA, data); in aplspi_transfer()
258 HWRITE4(sc, SPI_CONFIG, SPI_CONFIG_EN); in aplspi_transfer()
[all …]
H A Daplsart.c50 #define HWRITE4(sc, reg, val) \ macro
143 HWRITE4(sc, SART2_ADDR(i), addr >> SART_ADDR_SHIFT); in aplsart2_map()
144 HWRITE4(sc, SART2_CONFIG(i), in aplsart2_map()
163 HWRITE4(sc, SART3_ADDR(i), addr >> SART_ADDR_SHIFT); in aplsart3_map()
164 HWRITE4(sc, SART3_SIZE(i), size >> SART_SIZE_SHIFT); in aplsart3_map()
165 HWRITE4(sc, SART3_CONFIG(i), SART3_CONFIG_FLAGS_ALLOW); in aplsart3_map()
201 HWRITE4(sc, SART2_ADDR(i), 0); in aplsart2_unmap()
202 HWRITE4(sc, SART2_CONFIG(i), 0); in aplsart2_unmap()
218 HWRITE4(sc, SART3_ADDR(i), 0); in aplsart3_unmap()
219 HWRITE4(sc, SART3_SIZE(i), 0); in aplsart3_unmap()
[all …]
H A Dapldma.c74 #define HWRITE4(sc, reg, val) \ macro
233 HWRITE4(sc, DMA_TX_DESC_WRITE(ac->ac_chan), addr); in apldma_fill_descriptors()
234 HWRITE4(sc, DMA_TX_DESC_WRITE(ac->ac_chan), addr >> 32); in apldma_fill_descriptors()
384 HWRITE4(sc, DMA_TX_BUS_WIDTH(ac->ac_chan), in apldma_trigger_output()
388 HWRITE4(sc, DMA_TX_BUS_WIDTH(ac->ac_chan), in apldma_trigger_output()
398 HWRITE4(sc, DMA_TX_CTL(ac->ac_chan), 0); in apldma_trigger_output()
401 HWRITE4(sc, DMA_TX_INTRSTAT(ac->ac_chan, sc->sc_irq), in apldma_trigger_output()
403 HWRITE4(sc, DMA_TX_INTRMASK(ac->ac_chan, sc->sc_irq), in apldma_trigger_output()
409 HWRITE4(sc, DMA_TX_EN, 1 << (ac->ac_chan / 2)); in apldma_trigger_output()
420 HWRITE4(sc, DMA_TX_EN_CLR, 1 << (ac->ac_chan / 2)); in apldma_halt_output()
[all …]
H A Dapldog.c46 #define HWRITE4(sc, reg, val) \ macro
99 HWRITE4(sc, WDT_CHIP_CTL, 0); in apldog_attach()
100 HWRITE4(sc, WDT_SYS_CTL, 0); in apldog_attach()
113 HWRITE4(sc, WDT_SYS_RST, WDT_SYS_RST_IMMEDIATE); in apldog_reset()
114 HWRITE4(sc, WDT_SYS_CTL, WDT_SYS_CTL_ENABLE); in apldog_reset()
115 HWRITE4(sc, WDT_SYS_TMR, 0); in apldog_reset()
/openbsd/sys/arch/armv7/exynos/
H A Dexiic.c95 #define HWRITE4(sc, reg, val) \ macro
98 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
100 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
202 HWRITE4(sc, I2C_CON, sc->frequency); in exiic_setspeed()
230 HWRITE4(sc, I2C_STAT, 0); in exiic_i2c_acquire_bus()
231 HWRITE4(sc, I2C_ADD, 0); in exiic_i2c_acquire_bus()
232 HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_TX in exiic_i2c_acquire_bus()
270 HWRITE4(sc, I2C_DS, addr); in exiic_i2c_exec()
287 HWRITE4(sc, I2C_DS, ((uint8_t *)cmdbuf)[i]); in exiic_i2c_exec()
298 HWRITE4(sc, I2C_DS, addr); in exiic_i2c_exec()
[all …]

12345