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Searched refs:INSERT_VECTOR_ELT (Results 1 – 25 of 35) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp704 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
737 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
745 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
H A DREADME_ALTIVEC.txt314 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
H A DPPCISelLowering.cpp854 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
937 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in PPCTargetLowering()
1185 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
1186 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
1287 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
1288 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
1289 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
1290 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
1292 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
1293 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h523 INSERT_VECTOR_ELT, enumerator
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp432 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
436 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp61 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
965 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
1719 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
1723 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
3898 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
4232 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in CollectOpsToWiden()
5085 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
6533 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE()
6570 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE_SEQ()
6710 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
H A DSelectionDAGDumper.cpp295 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
H A DLegalizeDAG.cpp3058 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
4488 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { in PromoteNode()
4989 case ISD::INSERT_VECTOR_ELT: { in PromoteNode()
5032 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
H A DLegalizeIntegerTypes.cpp118 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
1645 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
4828 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
5603 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp148 setOperationAction(ISD::INSERT_VECTOR_ELT, in R600TargetLowering()
202 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD}); in R600TargetLowering()
402 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
665 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1769 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
H A DSIISelLowering.cpp274 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
304 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
318 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
332 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
346 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
547 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
772 ISD::INSERT_VECTOR_ELT}); in SITargetLowering()
4718 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
5028 case ISD::INSERT_VECTOR_ELT: { in ReplaceNodeResults()
10191 case ISD::INSERT_VECTOR_ELT: { in isCanonicalized()
[all …]
/openbsd/gnu/llvm/llvm/utils/
H A Dupdate_mir_test_checks.py301 INSERT_VECTOR_ELT='IVEC',
/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVEISelLowering.cpp318 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
335 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1842 return CDAG.getNode(ISD::INSERT_VECTOR_ELT, ResultVT, {AccuV, ElemV, IdxV}); in lowerBUILD_VECTOR()
1918 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
3169 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in lowerINSERT_VECTOR_ELT()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp171 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
253 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
396 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
445 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
1015 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, in ARMTargetLowering()
7757 Base = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Base, V, in LowerBUILD_VECTOR_i1()
8009 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); in LowerBUILD_VECTOR()
8732 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, VInput, Elt, in LowerVECTOR_SHUFFLEUsingOneOff()
9154 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp151 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::f16, Custom); in initializeHVXLowering()
232 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
389 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
1787 SDValue T0 = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in LowerHvxInsertElement()
3206 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1643 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1692 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
3338 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp208 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1418 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
2183 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp322 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
376 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
1954 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2517 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp365 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
506 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
507 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
5422 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
5494 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, in lowerSCALAR_TO_VECTOR()
5524 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, in lowerINSERT_VECTOR_ELT()
5795 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
6838 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) { in combineBSWAP()
6863 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT, in combineBSWAP()
H A DSystemZOperators.td294 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
H A DSystemZISelDAGToDAG.cpp1627 case ISD::INSERT_VECTOR_ELT: { in Select()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp524 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
547 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
643 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
712 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
821 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
938 ISD::VECTOR_SHUFFLE, ISD::INSERT_VECTOR_ELT, in RISCVTargetLowering()
2441 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntegerViaVecVT, Vec, in lowerBUILD_VECTOR()
2457 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntegerViaVecVT, Vec, Elt, in lowerBUILD_VECTOR()
2693 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, in lowerBUILD_VECTOR()
3851 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1307 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in AArch64TargetLowering()
1576 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
1768 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForStreamingSVE()
1887 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForFixedLengthSVE()
5903 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
11607 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()
12449 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, NewVector, in LowerBUILD_VECTOR()
17974 InitVal = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ReduceVT, in combineSVEReductionOrderedFP()
18715 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
21518 case ISD::INSERT_VECTOR_ELT: in PerformDAGCombine()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp920 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in X86TargetLowering()
1105 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1643 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
2361 ISD::INSERT_VECTOR_ELT, in X86TargetLowering()
8458 case ISD::INSERT_VECTOR_ELT: { in getFauxShuffleMask()
8909 if (Opcode == ISD::INSERT_VECTOR_ELT && in getShuffleScalarElt()
45234 Use->getOpcode() == ISD::INSERT_VECTOR_ELT || in combineExtractVectorElt()
48404 Opcode == ISD::INSERT_VECTOR_ELT) && in combineVectorInsert()
48592 if (IVEN.getOpcode() != ISD::INSERT_VECTOR_ELT || in combineAndShuffleNot()
51958 case ISD::INSERT_VECTOR_ELT: { in isFNEG()
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td464 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
714 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",

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