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Searched refs:IO_ICU2 (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/arch/amd64/amd64/
H A Di8259.c127 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ in i8259_default_setup()
129 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ in i8259_default_setup()
130 outb(IO_ICU2+1, IRQ_SLAVE); in i8259_default_setup()
132 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ in i8259_default_setup()
134 outb(IO_ICU2+1, 1); /* 8086 mode */ in i8259_default_setup()
136 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ in i8259_default_setup()
137 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ in i8259_default_setup()
138 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ in i8259_default_setup()
152 port = IO_ICU2 + 1; in i8259_hwmask()
174 port = IO_ICU2 + 1; in i8259_hwunmask()
[all …]
H A Dvector.S1001 #define ICUADDR IO_ICU2
/openbsd/sys/arch/loongson/loongson/
H A Dgeneric2e_machdep.c257 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = in generic2e_isa_intr()
259 ocw2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3); in generic2e_isa_intr()
546 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) = in via686sb_setup()
548 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8); in via686sb_setup()
549 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2); in via686sb_setup()
550 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086; in via686sb_setup()
552 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff; in via686sb_setup()
554 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = in via686sb_setup()
557 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR; in via686sb_setup()
H A Dgeneric3a_machdep.c413 REGVAL8(HTB_IO_BASE + IO_ICU2 + PIC_ICW1) = ICW1_SELECT | ICW1_IC4; in rs780sb_setup()
414 REGVAL8(HTB_IO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8); in rs780sb_setup()
415 REGVAL8(HTB_IO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(IRQ_CASCADE); in rs780sb_setup()
416 REGVAL8(HTB_IO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086; in rs780sb_setup()
417 REGVAL8(HTB_IO_BASE + IO_ICU2 + PIC_OCW1) = 0xff; in rs780sb_setup()
473 REGVAL8(HTB_IO_BASE + IO_ICU2 + PIC_OCW2) = in rs780e_eoi()
490 REGVAL8(HTB_IO_BASE + IO_ICU2 + PIC_OCW1) = imr2; in rs780e_set_imask()
H A Disa_machdep.c65 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = imr2; in loongson_set_isa_imr()
75 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW2) = in loongson_isa_specific_eoi()
H A Dyeeloong_machdep.c310 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = 0xff; in lemote_isa_attach_hook()
311 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 2) = 0xff; in lemote_isa_attach_hook()
447 imr2 = 0xff & ~REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1); in lemote_get_isa_imr()
458 isr2 = 0xff & REGVAL8(BONITO_PCIIO_BASE + IO_ICU2); in lemote_get_isa_isr()
/openbsd/usr.sbin/vmd/
H A Di8259.c597 case IO_ICU2: in i8259_io_write()
598 case IO_ICU2 + 1: in i8259_io_write()
606 if (port == IO_ICU1 + 1 || port == IO_ICU2 + 1) in i8259_io_write()
636 case IO_ICU2: in i8259_io_read()
637 case IO_ICU2 + 1: in i8259_io_read()
645 if (port == IO_ICU1 + 1 || port == IO_ICU2 + 1) in i8259_io_read()
H A Dx86_vm.c370 ioports_map[IO_ICU2] = vcpu_exit_i8259; in init_emulated_hw()
371 ioports_map[IO_ICU2 + 1] = vcpu_exit_i8259; in init_emulated_hw()
429 ioports_map[IO_ICU2] = vcpu_exit_i8259; in restore_emulated_hw()
430 ioports_map[IO_ICU2 + 1] = vcpu_exit_i8259; in restore_emulated_hw()
/openbsd/sys/arch/i386/isa/
H A Disa_machdep.c189 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ in isa_defaultirq()
190 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ in isa_defaultirq()
191 outb(IO_ICU2+1, IRQ_SLAVE); in isa_defaultirq()
193 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ in isa_defaultirq()
195 outb(IO_ICU2+1, 1); /* 8086 mode */ in isa_defaultirq()
197 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ in isa_defaultirq()
198 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ in isa_defaultirq()
199 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ in isa_defaultirq()
/openbsd/sys/arch/i386/include/
H A Di8259.h50 #define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
108 outb %al,$IO_ICU2 /* do the second ICU first */ ;\
/openbsd/sys/dev/isa/
H A Disareg.h60 #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ macro
/openbsd/sys/arch/amd64/include/
H A Di8259.h108 outb %al,$IO_ICU2 /* do the second ICU first */ ;\
/openbsd/sys/arch/i386/i386/
H A Dvector.s182 #define ICUADDR IO_ICU2
/openbsd/sys/arch/alpha/pci/
H A Dsio_pic.c352 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))