Searched refs:InitReg (Results 1 – 3 of 3) sorted by relevance
| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 1471 if (InitReg) { in phi()
1472 auto I = Phis.find({LoopReg, *InitReg}); in phi()
1487 if (!InitReg) in phi()
1493 MI->getOperand(1).setReg(*InitReg); in phi()
1494 Phis.insert({{LoopReg, *InitReg}, R}); in phi()
1496 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1507 if (InitReg) { in phi()
1509 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1514 .addReg(InitReg ? *InitReg : undef(RC)) in phi()
1518 if (!InitReg) in phi()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | R600MachineCFGStructurizer.cpp | 1287 Register InitReg = in improveSimpleJumpintoIf() local
1289 insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET, InitReg, in improveSimpleJumpintoIf()
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| H A D | SIISelLowering.cpp | 3622 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
3638 .addReg(InitReg) in emitLoadM0FromVGPRLoop()
3870 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
3872 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg); in emitIndirectSrc()
3875 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, in emitIndirectSrc()
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