| /openbsd/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 158 bool IsStore = false; in emitInstruction() local
160 &IsStore); in emitInstruction()
166 bool MaskAfter = IsSPFirstOperand && !IsStore; in emitInstruction()
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
212 if (IsStore) in isBasePlusOffsetMemoryAccess()
213 *IsStore = false; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
251 if (IsStore) in isBasePlusOffsetMemoryAccess()
252 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| H A D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
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| /openbsd/gnu/llvm/llvm/tools/llvm-reduce/deltas/ |
| H A D | ReduceOpcodes.cpp | 78 const bool IsStore = CB->getType()->isVoidTy(); in callLooksLikeLoadStore() local
93 if (!IsStore && !PT->isOpaqueOrPointeeTypeMatches(CB->getType())) in callLooksLikeLoadStore()
100 if (!IsStore || DataArg) in callLooksLikeLoadStore()
106 if (IsStore && !DataArg) { in callLooksLikeLoadStore()
124 if (IsStore && DataArg->getType()->getPointerTo( in callLooksLikeLoadStore()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 75 unsigned int IsStore : 1; member
367 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
373 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
683 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
700 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
705 if (SwapVector[UseOfUseIdx].IsStore) { in recordUnoptimizableWebs()
722 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
730 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
796 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
1008 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
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| /openbsd/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kCollapseMOVEMPass.cpp | 204 bool IsStore = false) { in ProcessMI() argument
209 if (State.isStore() == IsStore && State.getBase() == Reg && in ProcessMI()
218 return ProcessMI(MBB, MI, State, Mask, Offset, Reg, IsStore); in ProcessMI()
227 IsStore ? State.setStore() : State.setLoad(); in ProcessMI()
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| /openbsd/gnu/llvm/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrFormats.td | 36 bit IsStore = false;
52 let TSFlags{6...6} = IsStore;
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| /openbsd/gnu/llvm/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 406 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
413 if (IsStore && MI->mayLoad()) in canHoistLoadStoreTo()
455 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
465 if (IsStore) { in changeToAddrMode()
472 if (IsStore) in changeToAddrMode()
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| /openbsd/gnu/llvm/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 838 bit IsStore = ?;
1146 let IsStore = true;
1151 let IsStore = true;
1158 let IsStore = true;
1163 let IsStore = true;
1169 let IsStore = true;
1175 let IsStore = true;
1181 let IsStore = true;
1186 let IsStore = true;
1191 let IsStore = true;
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1203 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
1207 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1208 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1240 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
1243 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
1272 bool IsStore = TII->get(LoadStoreOp).mayStore(); in getFlatScratchSpillOpcode() local
1279 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in getFlatScratchSpillOpcode()
1319 bool IsStore = Desc->mayStore(); in buildSpillLoadStore() local
1525 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
1536 bool NeedSuperRegDef = e > 1 && IsStore && IsFirstSubReg; in buildSpillLoadStore()
[all …]
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| H A D | AMDGPUInstructions.td | 422 let IsStore = 1;
506 let IsStore = 1, AddressSpaces = !cast<AddressSpaceList>("StoreAddress_"#as).AddrSpaces in {
531 } // End let IsStore = 1, AddressSpaces = ...
657 let IsStore = 1;
662 let IsStore = 1;
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| H A D | SIInstrInfo.td | 509 let IsStore = 1;
515 let IsStore = 1;
521 let IsStore = 1;
527 let IsStore = 1;
534 let IsStore = 1;
551 let IsStore = 1;
557 let IsStore = 1;
577 let IsStore = 1;
583 let IsStore = 1;
648 let IsStore = 1;
[all …]
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| H A D | AMDGPULegalizerInfo.cpp | 1145 const bool IsStore = Op == G_STORE; in AMDGPULegalizerInfo() local
1200 if (!IsStore) { in AMDGPULegalizerInfo()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 147 const bool IsStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreOp() local
152 return IsStore ? PPC::STW : PPC::LWZ; in selectLoadStoreOp()
154 return IsStore ? PPC::STD : PPC::LD; in selectLoadStoreOp()
162 return IsStore ? PPC::STFS : PPC::LFS; in selectLoadStoreOp()
164 return IsStore ? PPC::STFD : PPC::LFD; in selectLoadStoreOp()
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| /openbsd/gnu/llvm/llvm/utils/TableGen/ |
| H A D | X86FoldTablesEmitter.cpp | 108 bool IsStore = false; member in __anon12122ca80111::X86FoldTablesEmitter::X86FoldTableEntry
126 if (IsStore) in print()
413 Result.IsStore = true; in addEntryWithFlags()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 464 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
465 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
466 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
483 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
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| H A D | ARMLoadStoreOptimizer.cpp | 502 bool IsStore = in UpdateBaseRegUses() local
505 if (IsLoad || IsStore) { in UpdateBaseRegUses()
518 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base)) in UpdateBaseRegUses()
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| /openbsd/gnu/llvm/clang/include/clang/Basic/ |
| H A D | arm_sve.td | 186 def IsStore : FlagType<0x00004000>;
549 def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch6…
550 def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore], MemEltTyInt8, "aarch6…
551 def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore], MemEltTyInt8, "aarch6…
552 def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore], MemEltTyInt16, "aarch6…
553 def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore], MemEltTyInt16, "aarch6…
554 def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore], MemEltTyInt32, "aarch6…
555 def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore], MemEltTyInt32, "aarch6…
567 …def SVST1_BF : MInst<"svst1[_{d}]", "vPpd", "b", [IsStore], MemEltTyDefault, "aarch64_s…
568 …def SVST1_VNUM_BF : MInst<"svst1_vnum[_{d}]", "vPpld", "b", [IsStore], MemEltTyDefault, "aarch64_s…
[all …]
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| H A D | TargetBuiltins.h | 273 bool isStore() const { return Flags & IsStore; } in isStore()
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| /openbsd/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 1344 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1367 if (IsStore) in EmitAtomicExpr()
1379 if (IsLoad || IsStore) in EmitAtomicExpr()
1404 if (!IsStore) in EmitAtomicExpr()
1408 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1425 if (!IsStore) { in EmitAtomicExpr()
1443 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 844 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
845 if (!IsLoad && !IsStore) in canMoveMemTo()
866 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
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| H A D | HexagonConstExtenders.cpp | 1148 bool IsStore = MI.mayStore(); in recordExtender() local
1157 if (IsLoad || IsStore) { in recordExtender()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 382 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() local
383 unsigned AddrBase = IsStore; in SimplifyShortMoveForm()
384 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm()
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| H A D | X86TargetTransformInfo.cpp | 4845 bool IsStore = (Instruction::Store == Opcode); in getMaskedMemoryOpCost() local
4856 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { in getMaskedMemoryOpCost()
4867 SrcVTy, DemandedElts, IsLoad, IsStore, CostKind); in getMaskedMemoryOpCost()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19592 bool IsStore = false; in performNEONPostLDSTCombine() local
19607 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
19609 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
19611 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
19619 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
19621 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
19623 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
19637 NumVecs = 2; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
19645 if (IsStore) in performNEONPostLDSTCombine()
19664 if (IsLaneOp || IsStore) in performNEONPostLDSTCombine()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1074 bool IsStore = Opcode == TargetOpcode::G_STORE; in applyCombineIndexedLoadStore() local
1094 if (IsStore) { in applyCombineIndexedLoadStore()
|