1 /* $OpenBSD: amdisplayreg.h,v 1.5 2019/05/06 03:45:58 mlarkin Exp $ */ 2 /* 3 * Copyright (c) 2016 Ian Sutton <ians@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* AM335x LCDC register offsets */ 19 #define LCD_PID 0x00 20 #define LCD_CTRL 0x04 21 #define LCD_CTRL_CLKDIV (0xFF << 8) 22 #define LCD_CTRL_AUTO_UFLOW_RESTART (1 << 1) 23 #define LCD_CTRL_MODESEL (1 << 0) 24 #define LCD_CTRL_CLKDIV_SHAMT 8 25 #define LCD_RASTER_CTRL 0x28 26 #define LCD_RASTER_CTRL_TFT24UNPACKED (1 << 26) 27 #define LCD_RASTER_CTRL_TFT24 (1 << 25) 28 #define LCD_RASTER_CTRL_STN565 (1 << 24) 29 #define LCD_RASTER_CTRL_TFTMAP (1 << 23) 30 #define LCD_RASTER_CTRL_NIBMODE (1 << 22) 31 #define LCD_RASTER_CTRL_PALMODE (3 << 20) 32 #define LCD_RASTER_CTRL_REQDLY (0xFF << 12) 33 #define LCD_RASTER_CTRL_LCDTFT (1 << 7) 34 #define LCD_RASTER_CTRL_LCDEN (1 << 0) 35 #define LCD_RASTER_CTRL_PALMODE_SHAMT 20 36 #define LCD_RASTER_CTRL_REQDLY_SHAMT 12 37 #define LCD_RASTER_TIMING_0 0x2C 38 #define LCD_RASTER_TIMING_0_HBP (0xFF << 24) 39 #define LCD_RASTER_TIMING_0_HFP (0xFF << 16) 40 #define LCD_RASTER_TIMING_0_HSW (0x3F << 10) 41 #define LCD_RASTER_TIMING_0_PPLLSB (0x3 << 4) 42 #define LCD_RASTER_TIMING_0_PPLMSB (0x1 << 3) 43 #define LCD_RASTER_TIMING_0_HBP_SHAMT 24 44 #define LCD_RASTER_TIMING_0_HFP_SHAMT 16 45 #define LCD_RASTER_TIMING_0_HSW_SHAMT 10 46 #define LCD_RASTER_TIMING_0_PPLLSB_SHAMT 4 47 #define LCD_RASTER_TIMING_0_PPLMSB_SHAMT 3 48 #define LCD_RASTER_TIMING_1 0x30 49 #define LCD_RASTER_TIMING_1_VBP (0xFF << 24) 50 #define LCD_RASTER_TIMING_1_VFP (0xFF << 16) 51 #define LCD_RASTER_TIMING_1_VSW (0x3C << 10) 52 #define LCD_RASTER_TIMING_1_LPP (0x3FF << 0) 53 #define LCD_RASTER_TIMING_1_VBP_SHAMT 24 54 #define LCD_RASTER_TIMING_1_VFP_SHAMT 16 55 #define LCD_RASTER_TIMING_1_VSW_SHAMT 10 56 #define LCD_RASTER_TIMING_2 0x34 57 #define LCD_RASTER_TIMING_2_HSW_HIGHBITS (0xF << 27) 58 #define LCD_RASTER_TIMING_2_LPP_B10 (0x1 << 26) 59 #define LCD_RASTER_TIMING_2_PHSVS_ON_OFF (0x1 << 25) 60 #define LCD_RASTER_TIMING_2_PHSVS_RF (0x1 << 24) 61 #define LCD_RASTER_TIMING_2_IEO (0x1 << 23) 62 #define LCD_RASTER_TIMING_2_IPC (0x1 << 22) 63 #define LCD_RASTER_TIMING_2_IHS (0x1 << 21) 64 #define LCD_RASTER_TIMING_2_IVS (0x1 << 20) 65 #define LCD_RASTER_TIMING_2_ACBI (0xF << 16) 66 #define LCD_RASTER_TIMING_2_ACB (0xFF << 8) 67 #define LCD_RASTER_TIMING_2_HBP_HIGHBITS (0x3 << 4) 68 #define LCD_RASTER_TIMING_2_HFP_HIGHBITS (0x3 << 0) 69 #define LCD_RASTER_TIMING_2_HSW_HIGHBITS_SHAMT 27 70 #define LCD_RASTER_TIMING_2_LPP_B10_SHAMT 26 71 #define LCD_RASTER_TIMING_2_ACBI_SHAMT 16 72 #define LCD_RASTER_TIMING_2_ACB_SHAMT 8 73 #define LCD_RASTER_TIMING_2_HPB_HIGHBITS_SHAMT 4 74 #define LCD_RASTER_SUBPANEL 0x38 75 #define LCD_RASTER_SUBPANEL_SPEN (0x1 << 31) 76 #define LCD_RASTER_SUBPANEL_HOLS (0x1 << 29) 77 #define LCD_RASTER_SUBPANEL_LPPT (0x2FF << 16) 78 #define LCD_RASTER_SUBPANEL_DPDLSB (0xFFFF << 0) 79 #define LCD_RASTER_SUBPANEL_LPPT_SHAMT 80 #define LCD_RASTER_SUBPANEL_2 0x3C 81 #define LCD_RASTER_SUBPANEL2_LPPT_B10 (0x1 << 8) 82 #define LCD_RASTER_SUBPANEL2_DPDMSB (0xFF << 0) 83 #define LCD_LCDDMA_CTRL 0x40 84 #define LCD_LCDDMA_CTRL_DMA_MASTER_PRIO (0x7 << 0x10) 85 #define LCD_LCDDMA_CTRL_TH_FIFO_READY (0x7 << 0x08) 86 #define LCD_LCDDMA_CTRL_BURST_SIZE (0x7 << 0x04) 87 #define LCD_LCDDMA_CTRL_BYTE_SWAP (0x1 << 0x03) 88 #define LCD_LCDDMA_CTRL_BIGENDIAN (0x1 << 0x01) 89 #define LCD_LCDDMA_CTRL_FRAME_MODE (0x1 << 0x00) 90 #define LCD_LCDDMA_CTRL_DMA_MASTER_PRIO_SHAMT 0xFF 91 #define LCD_LCDDMA_CTRL_TH_FIFO_READY_SHAMT 0x08 92 #define LCD_LCDDMA_CTRL_BURST_SIZE_SHAMT 0x04 93 #define LCD_LCDDMA_FB0 0x44 94 #define LCD_LCDDMA_FB0_BASE 0xFFFC 95 #define LCD_LCDDMA_FB0_BASE_SHAMT 0 96 #define LCD_LCDDMA_FB0_CEIL 0x48 97 #define LCD_LCDDMA_FB0_CEILING 0xFFFC 98 #define LCD_LCDDMA_FB0_CEILING_SHAMT 0 99 #define LCD_LCDDMA_FB1 0x4C 100 #define LCD_LCDDMA_FB1_BASE 0xFFFC 101 #define LCD_LCDDMA_FB1_BASE_SHAMT 0 102 #define LCD_LCDDMA_FB1_CEIL 0x50 103 #define LCD_LCDDMA_FB1_CEILING 0xFFFC 104 #define LCD_LCDDMA_FB1_CEILING_SHAMT 0 105 #define LCD_SYSCONFIG 0x54 106 #define LCD_SYSCONFIG_STANDBYMODE (2 << 4) 107 #define LCD_SYSCONFIG_IDLEMODE (2 << 2) 108 #define LCD_SYSCONFIG_STANDBYMODE_SHAMT 4 109 #define LCD_SYSCONFIG_IDLEMODE_SHAMT 2 110 #define LCD_IRQSTATUS_RAW 0x58 111 #define LCD_IRQSTATUS 0x5C 112 #define LCD_IRQENABLE_SET 0x60 113 #define LCD_IRQENABLE_CLEAR 0x64 114 #define LCD_IRQ_END 0x68 115 #define LCD_CLKC_ENABLE 0x6C 116 #define LCD_CLKC_ENABLE_DMA_CLK_EN (1 << 2) 117 #define LCD_CLKC_ENABLE_LIDD_CLK_EN (1 << 1) 118 #define LCD_CLKC_ENABLE_CORE_CLK_EN (1 << 0) 119 #define LCD_CLKC_RESET 0x70 120 #define LCD_CLKC_RESET_MAIN_RST (1 << 3) 121 #define LCD_CLKC_RESET_DMA_RST (1 << 2) 122 #define LCD_CLKC_RESET_LIDD_RST (1 << 1) 123 #define LCD_CLKC_RESET_CORE_RST (1 << 0) 124 125 /* AM335x LCDC intr. masks */ 126 #define LCD_IRQ_EOF1 (1 << 9) 127 #define LCD_IRQ_EOF0 (1 << 8) 128 #define LCD_IRQ_PL (1 << 6) 129 #define LCD_IRQ_FUF (1 << 5) 130 #define LCD_IRQ_ACB (1 << 3) 131 #define LCD_IRQ_SYNC (1 << 2) 132 #define LCD_IRQ_RR_DONE (1 << 1) 133 #define LCD_IRQ_DONE (1 << 0) 134 135 /* EDID reading */ 136 #define EDID_LENGTH 0x80 137 138 /* phandle for pin muxing */ 139 #define LCD_FDT_PHANDLE 0x2f 140