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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK (Results 1 – 12 of 12) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7630 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L macro
H A Ddce_8_0_sh_mask.h3187 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 macro
H A Ddce_10_0_sh_mask.h3109 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 macro
H A Ddce_11_0_sh_mask.h3179 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 macro
H A Ddce_11_2_sh_mask.h3427 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 macro
H A Ddce_12_0_sh_mask.h9262 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21259 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … macro
H A Ddcn_1_0_sh_mask.h40013 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … macro
H A Ddcn_2_1_0_sh_mask.h43247 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h42529 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h48756 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h49125 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … macro