| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3652 bool LegalOps; member
3658 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} in TargetLoweringOpt()
3661 bool LegalOperations() const { return LegalOps; } in LegalOperations()
4076 bool LegalOps, bool OptForSize,
4081 SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize,
4086 getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
4102 bool LegalOps, bool OptForSize,
4104 return getCheaperOrNeutralNegatedExpression(Op, DAG, LegalOps, OptForSize,
4110 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
4113 return getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2154 if (DemandedBits.isOne() && !TLO.LegalOps && !VT.isVector()) in SimplifyDemandedBits()
3253 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { in SimplifyDemandedVectorElts()
6814 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6844 if (LegalOps && !IsOpLegal) in getNegatedExpression()
6865 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
6872 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6880 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6928 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
6936 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
6973 getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth); in getNegatedExpression()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 826 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
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| H A D | PPCISelLowering.cpp | 17080 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
17103 getNegatedExpression(N2, DAG, LegalOps, OptForSize, N2Cost, Depth + 1); in getNegatedExpression()
17115 SDValue NegN0 = getNegatedExpression(N0, DAG, LegalOps, OptForSize, in getNegatedExpression()
17119 SDValue NegN1 = getNegatedExpression(N1, DAG, LegalOps, OptForSize, in getNegatedExpression()
17140 return TargetLowering::getNegatedExpression(Op, DAG, LegalOps, OptForSize, in getNegatedExpression()
17587 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike() local
17600 if (SDValue NegN0 = getCheaperNegatedExpression(N0, DAG, LegalOps, CodeSize)) in combineFMALike()
17605 if (SDValue NegN1 = getCheaperNegatedExpression(N1, DAG, LegalOps, CodeSize)) in combineFMALike()
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| /openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 934 if (Op.getOpcode() == ISD::BUILD_VECTOR && TLO.LegalOps && TLO.LegalTys) in shouldSimplifyDemandedVectorElts()
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 10698 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 19964 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2072 if (!TLO.LegalOps) in targetShrinkDemandedConstant()
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