Searched refs:LegalVecVT (Results 1 – 3 of 3) sorted by relevance
| /openbsd/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VVPISelLowering.cpp | 60 EVT LegalVecVT = getTypeToTransformTo(*DAG.getContext(), OpVecVT); in lowerToVVP() local
61 auto Packing = getTypePacking(LegalVecVT.getSimpleVT()); in lowerToVVP()
82 assert(LegalVecVT.isSimple()); in lowerToVVP()
84 return CDAG.getNode(VVPOpcode, LegalVecVT, {Op->getOperand(0), Mask, AVL}); in lowerToVVP()
86 return CDAG.getNode(VVPOpcode, LegalVecVT, in lowerToVVP()
105 return CDAG.getNode(VVPOpcode, LegalVecVT, {X, Y, Z, Mask, AVL}); in lowerToVVP()
111 return CDAG.getNode(VVPOpcode, LegalVecVT, {OnTrue, OnFalse, Mask, AVL}); in lowerToVVP()
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| H A D | VEISelLowering.cpp | 316 for (MVT LegalVecVT : AllVectorVTs) { in initVPUActions() local
317 setOperationAction(ISD::BUILD_VECTOR, LegalVecVT, Custom); in initVPUActions()
318 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
319 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
326 setOperationAction(ISD::VP_OPC, LegalVecVT, Custom); in initVPUActions()
328 setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom); in initVPUActions()
329 setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, LegalVecVT, Custom); in initVPUActions()
330 setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, LegalVecVT, Custom); in initVPUActions()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13224 EVT LegalVecVT = MVT::getVectorVT(ScalarType, LegalLanes); in PerformVQDMULHCombine() local
13235 Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0); in PerformVQDMULHCombine()
13236 Inp1 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp1); in PerformVQDMULHCombine()
13237 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
13249 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext0.getOperand(0), in PerformVQDMULHCombine()
13252 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext1.getOperand(0), in PerformVQDMULHCombine()
13254 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
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