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Searched refs:MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT (Results 1 – 17 of 17) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7674 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000 macro
H A Ddce_8_0_sh_mask.h8154 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h7218 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h7108 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h8220 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 macro
H A Ddce_12_0_sh_mask.h5119 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1750 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_1_0_sh_mask.h4138 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h2644 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h2845 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h2329 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h1686 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h10959 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h2896 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h2805 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h2912 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h2902 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … macro