Home
last modified time | relevance | path

Searched refs:MMHUB_HWIP (Results 1 – 17 of 17) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dmmhub_v2_0.c154 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_print_l2_protection_fault_status()
571 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
604 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
628 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_light_sleep()
654 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_set_clockgating()
679 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_get_clockgating()
H A Ddimgrey_cavefish_reg_init.c37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
H A Dvega10_reg_init.c36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
H A Damdgpu_discovery.c188 [MMHUB_HWIP] = MMHUB_HWID,
2180 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2202 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); in amdgpu_discovery_set_ip_blocks()
2226 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); in amdgpu_discovery_set_ip_blocks()
2242 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); in amdgpu_discovery_set_ip_blocks()
2263 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); in amdgpu_discovery_set_ip_blocks()
2287 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); in amdgpu_discovery_set_ip_blocks()
2315 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); in amdgpu_discovery_set_ip_blocks()
H A Dvega20_reg_init.c36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
H A Dgmc_v11_0.c207 GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_vm_hub()
613 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v11_0_set_mmhub_funcs()
H A Dgmc_v9_0.c673 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_process_interrupt()
1502 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_set_mmhub_funcs()
1520 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_set_mmhub_ras_funcs()
2252 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_init_golden_registers()
H A Dgmc_v10_0.c246 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
700 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v10_0_set_mmhub_funcs()
H A Dmmhub_v3_0_1.c111 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v3_0_1_print_l2_protection_fault_status()
H A Dmmhub_v2_3.c93 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_3_print_l2_protection_fault_status()
H A Dmmhub_v3_0.c110 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v3_0_print_l2_protection_fault_status()
H A Damdgpu_virt.c968 case MMHUB_HWIP: in amdgpu_virt_get_rlcg_reg_access_flag()
H A Dmes_v10_1.c306 adev->reg_offset[MMHUB_HWIP][0][i]; in mes_v10_1_set_hw_resources()
H A Dmes_v11_0.c397 adev->reg_offset[MMHUB_HWIP][0][i]; in mes_v11_0_set_hw_resources()
H A Damdgpu.h651 MMHUB_HWIP, enumerator