Home
last modified time | relevance | path

Searched refs:MP1_HWIP (Results 1 – 25 of 27) sorted by relevance

12

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_reset.c41 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_reset_init()
63 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_reset_fini()
H A Daldebaran.c38 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && in aldebaran_is_mode2_default()
160 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && in aldebaran_mode2_perform_reset()
342 if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] == in aldebaran_mode2_restore_hwcontext()
H A Dsoc15.c327 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
328 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1) || in soc15_get_xclk()
329 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 6)) in soc15_get_xclk()
331 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
332 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
526 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_asic_reset_method()
625 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_supports_baco()
H A Ddimgrey_cavefish_reg_init.c41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
H A Damdgpu_discovery.c192 [MP1_HWIP] = MP1_HWID,
1825 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_discovery_set_smu_ip_blocks()
1866 adev->ip_versions[MP1_HWIP][0]); in amdgpu_discovery_set_smu_ip_blocks()
2190 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2212 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2235 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
2251 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2273 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2303 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2328 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
H A Dvega10_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
H A Dsienna_cichlid.c39 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7) && in sienna_cichlid_is_mode2_default()
H A Damdgpu_ucode.c1118 } else if (block_type == MP1_HWIP) { in amdgpu_ucode_legacy_naming()
1119 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1298 case MP1_HWIP: in amdgpu_ucode_ip_version_decode()
H A Damdgpu_ras_eeprom.c156 switch (adev->ip_versions[MP1_HWIP][0]) { in __is_ras_eeprom_supported()
194 switch (adev->ip_versions[MP1_HWIP][0]) { in __get_eeprom_i2c_addr()
H A Dsoc21.c376 switch (adev->ip_versions[MP1_HWIP][0]) { in soc21_asic_reset_method()
H A Dnv.c456 switch (adev->ip_versions[MP1_HWIP][0]) { in nv_asic_reset_method()
H A Damdgpu.h655 MP1_HWIP, enumerator
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c104 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) || in smu_v11_0_init_microcode()
105 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) in smu_v11_0_init_microcode()
216 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_check_fw_version()
249 adev->ip_versions[MP1_HWIP][0]); in smu_v11_0_check_fw_version()
734 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) || in smu_v11_0_init_display_count()
735 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) || in smu_v11_0_init_display_count()
736 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12) || in smu_v11_0_init_display_count()
737 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in smu_v11_0_init_display_count()
1106 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_gfx_off_control()
1596 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_baco_set_state()
[all …]
H A Dnavi10_ppt.c348 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
357 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
919 switch (adev->ip_versions[MP1_HWIP][0]) { in navi1x_get_smu_metrics_data()
929 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || in navi1x_get_smu_metrics_data()
1730 switch (adev->ip_versions[MP1_HWIP][0]) { in navi10_populate_umd_state_clk()
2772 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) || in navi10_need_umc_cdr_workaround()
2773 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) in navi10_need_umc_cdr_workaround()
2901 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) in navi10_run_umc_cdr_workaround()
2907 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) in navi10_run_umc_cdr_workaround()
3376 switch (adev->ip_versions[MP1_HWIP][0]) { in navi1x_get_gpu_metrics()
[all …]
H A Dsienna_cichlid_ppt.c77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in get_table_size()
312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_allowed_feature_mask()
437 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in sienna_cichlid_append_powerplay_table()
450 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in sienna_cichlid_append_powerplay_table()
728 switch (smu->adev->ip_versions[MP1_HWIP][0]) { in sienna_cichlid_get_smu_metrics_data()
1497 switch (adev->ip_versions[MP1_HWIP][0]) { in sienna_cichlid_populate_umd_state_clk()
1948 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) { in sienna_cichlid_read_sensor()
1957 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) { in sienna_cichlid_read_sensor()
3922 switch (smu->adev->ip_versions[MP1_HWIP][0]) { in sienna_cichlid_get_gpu_metrics()
[all …]
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dyellow_carp_ppt.c1027 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1029 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1030 (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1034 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1036 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1037 (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1041 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1043 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1044 (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
H A Dsmu_v13_0.c104 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); in smu_v13_0_init_microcode()
199 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) || in smu_v13_0_init_pptable_microcode()
200 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) || in smu_v13_0_init_pptable_microcode()
201 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))) in smu_v13_0_init_pptable_microcode()
237 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_check_fw_status()
272 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 6)) in smu_v13_0_check_fw_version()
805 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_gfx_off_control()
1785 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { in smu_v13_0_set_performance_level()
1932 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value)) in smu_v13_0_get_dpm_level_count()
1992 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) { in smu_v13_0_set_single_dpm_table()
H A Dsmu_v13_0_0_ppt.c2431 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_0_mode1_reset()
2464 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) in smu_v13_0_0_mode2_reset()
2476 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) in smu_v13_0_0_enable_gfx_features()
2540 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) && in smu_v13_0_0_check_ecc_table_support()
H A Dsmu_v13_0_4_ppt.c1159 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) in smu_v13_0_4_set_ppt_funcs()
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/
H A Damdgpu_smu.c466 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) in is_support_sw_smu()
584 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_set_funcs()
748 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || in smu_late_init()
749 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) in smu_late_init()
1232 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_smc_hw_setup()
1422 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { in smu_start_smc_engine()
1522 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
1543 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
1563 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
1580 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
[all …]
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1201 …if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) && (adev->pm.fw_version >= 0x40000f)… in renoir_get_smu_metrics_data()
1202 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0)) && (adev->pm.fw_version >= 0x373200))) in renoir_get_smu_metrics_data()
/openbsd/sys/dev/pci/drm/amd/pm/
H A Damdgpu_pm.c2006 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; in default_attr_update()
3470 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; in amdgpu_debugfs_pm_info_pp()

12