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Searched refs:MPLL_DQ_FUNC_CNTL (Results 1 – 16 of 16) sorted by relevance

/openbsd/sys/dev/pci/drm/radeon/
H A Drv740d.h63 #define MPLL_DQ_FUNC_CNTL 0x62c macro
H A Drv740_dpm.c307 RREG32(MPLL_DQ_FUNC_CNTL); in rv740_read_clock_registers()
H A Drv770d.h136 #define MPLL_DQ_FUNC_CNTL 0x62c macro
H A Dnid.h578 #define MPLL_DQ_FUNC_CNTL 0x62c macro
H A Dsid.h626 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
H A Dcikd.h749 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
H A Devergreend.h116 #define MPLL_DQ_FUNC_CNTL 0x62c macro
H A Drv770_dpm.c1537 RREG32(MPLL_DQ_FUNC_CNTL); in rv770_read_clock_registers()
H A Dni_dpm.c1191 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ni_read_clock_registers()
H A Dsi_dpm.c3561 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
H A Dci_dpm.c1852 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c1090 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in iceland_calculate_mclk_params()
1092 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
H A Dci_smumgr.c1064 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in ci_calculate_mclk_params()
1066 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
H A Dtonga_smumgr.c840 MPLL_DQ_FUNC_CNTL, YCLK_SEL, in tonga_calculate_mclk_params()
843 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, in tonga_calculate_mclk_params()
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dsid.h627 #define MPLL_DQ_FUNC_CNTL 0xAF1 macro
/openbsd/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Damdgpu_si_dpm.c4035 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()