/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86InstrShiftRotate.td | 565 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 568 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 571 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 574 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 580 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), 583 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), 591 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), 597 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 600 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 603 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), [all …]
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H A D | X86InstrSystem.td | 259 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 261 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 263 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 489 def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), 492 def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), 635 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 638 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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H A D | X86FixupGadgets.cpp | 317 case X86II::MRM1r: { in isROPFriendly() 325 if (isROPFriendlyReg(DstReg, Form == X86II::MRM1r ? 1 : 0)) in isROPFriendly()
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H A D | X86InstrFPStack.td | 351 def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 352 def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 353 def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 479 def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 487 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 633 def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">;
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H A D | X86InstrArithmetic.td | 489 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 492 def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 496 def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 500 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", 1196 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
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H A D | X86InstrInfo.td | 2522 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>; 2523 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, VEX_W; 2750 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; 2753 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; 2777 def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", 2782 def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", 2803 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
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H A D | X86InstrFormats.td | 52 def MRM0r : Format<48>; def MRM1r : Format<49>; def MRM2r : Format<50>;
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H A D | X86InstrAVX512.td | 6311 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli,
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/openbsd/gnu/llvm/llvm/utils/TableGen/ |
H A D | X86RecognizableInstr.h | 127 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, enumerator
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H A D | X86RecognizableInstr.cpp | 692 case X86Local::MRM1r: in emitInstructionSpecifier() 834 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
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H A D | X86FoldTablesEmitter.cpp | 367 (MemForm == X86Local::MRM1m && RegForm == X86Local::MRM1r) || in areOppositeForms()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86BaseInfo.h | 729 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3 enumerator 1145 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
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H A D | X86MCCodeEmitter.cpp | 1048 case X86II::MRM1r: in emitVEXOpcodePrefix() 1221 case X86II::MRM1r: in emitREXPrefix() 1603 case X86II::MRM1r: in encodeInstruction()
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/openbsd/gnu/llvm/llvm/tools/llvm-exegesis/lib/X86/ |
H A D | Target.cpp | 81 case X86II::MRM1r: in isInvalidMemoryInstr()
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/openbsd/gnu/llvm/llvm/docs/ |
H A D | WritingAnLLVMBackend.rst | 1902 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
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