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Searched refs:NUM_MP0CLK_DPM_LEVELS (Results 1 – 11 of 11) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu9_driver_if.h40 #define NUM_MP0CLK_DPM_LEVELS 8 macro
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
193 uint8_t Mp0clkDid[NUM_MP0CLK_DPM_LEVELS]; /* DID */
194 uint8_t Mp0DpmVoltageIndex[NUM_MP0CLK_DPM_LEVELS];
H A Dsmu11_driver_if.h40 #define NUM_MP0CLK_DPM_LEVELS 2 macro
55 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
435 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
436 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h39 #define NUM_MP0CLK_DPM_LEVELS 2 macro
52 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
322 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
323 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h37 #define NUM_MP0CLK_DPM_LEVELS 2 macro
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
525 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
526 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
H A Dsmu11_driver_if_sienna_cichlid.h37 #define NUM_MP0CLK_DPM_LEVELS 2 macro
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
705 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
706 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
1065 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
1066 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
H A Dsmu11_driver_if_navi10.h38 #define NUM_MP0CLK_DPM_LEVELS 2 macro
53 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
602 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
603 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
H A Dsmu13_driver_if_v13_0_0.h34 #define NUM_MP0CLK_DPM_LEVELS 2 macro
1056 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
1057 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
H A Dsmu13_driver_if_v13_0_7.h35 #define NUM_MP0CLK_DPM_LEVELS 2 macro
1065 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
1066 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_processpptables.c369 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
373 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.c1796 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
1800 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
H A Dsienna_cichlid_ppt.c2759 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
2763 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
3397 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
3401 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()