1 /* $OpenBSD: siopreg.h,v 1.12 2010/07/23 07:47:13 jsg Exp $ */ 2 /* $NetBSD: siopreg.h,v 1.16 2005/02/27 00:27:02 perry Exp $ */ 3 4 /* 5 * Copyright (c) 2000 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * Devices definitions for Symbios/NCR M53c8xx PCI-SCSI I/O Processors 31 * Docs available from http://www.symbios.com/ 32 */ 33 34 #define SIOP_SCNTL0 0x00 /* SCSI control 0, R/W */ 35 #define SCNTL0_ARB_MASK 0xc0 36 #define SCNTL0_SARB 0x00 37 #define SCNTL0_FARB 0xc0 38 #define SCNTL0_START 0x20 39 #define SCNTL0_WATM 0x10 40 #define SCNTL0_EPC 0x08 41 #define SCNTL0_AAP 0x02 42 #define SCNTL0_TRG 0x01 43 44 #define SIOP_SCNTL1 0x01 /* SCSI control 1, R/W */ 45 #define SCNTL1_EXC 0x80 46 #define SCNTL1_ADB 0x40 47 #define SCNTL1_DHP 0x20 48 #define SCNTL1_CON 0x10 49 #define SCNTL1_RST 0x08 50 #define SCNTL1_AESP 0x04 51 #define SCNTL1_IARB 0x02 52 #define SCNTL1_SST 0x01 53 54 #define SIOP_SCNTL2 0x02 /* SCSI control 2, R/W */ 55 #define SCNTL2_SDU 0x80 56 #define SCNTL2_CHM 0x40 /* 875 only */ 57 #define SCNTL2_SLPMD 0x20 /* 875 only */ 58 #define SCNTL2_SLPHBEN 0x10 /* 875 only */ 59 #define SCNTL2_WSS 0x08 /* 875 only */ 60 #define SCNTL2_VUE0 0x04 /* 875 only */ 61 #define SCNTL2_VUE1 0x02 /* 875 only */ 62 #define SCNTL2_WSR 0x01 /* 875 only */ 63 64 #define SIOP_SCNTL3 0x03 /* SCSI control 3, R/W */ 65 #define SCNTL3_ULTRA 0x80 /* 875 only */ 66 #define SCNTL3_SCF_SHIFT 4 67 #define SCNTL3_SCF_MASK 0x70 68 #define SCNTL3_EWS 0x08 /* 875 only */ 69 #define SCNTL3_CCF_SHIFT 0 70 #define SCNTL3_CCF_MASK 0x07 71 72 /* periods for various SCF values, assume transfer period of 4 */ 73 struct scf_period { 74 int clock; /* clock period (ns * 10) */ 75 int period; /* scsi period, as set in the SDTR message */ 76 int scf; /* scf value to use */ 77 }; 78 79 #ifdef SIOP_NEEDS_PERIOD_TABLES 80 static const struct scf_period scf_period[] = { 81 {250, 25, 1}, /* 10.0 MHz */ 82 {250, 37, 2}, /* 6.67 MHz */ 83 {250, 50, 3}, /* 5.00 MHz */ 84 {250, 75, 4}, /* 3.33 MHz */ 85 {125, 12, 1}, /* 20.0 MHz */ 86 {125, 18, 2}, /* 13.3 MHz */ 87 {125, 25, 3}, /* 10.0 MHz */ 88 {125, 37, 4}, /* 6.67 MHz */ 89 {125, 50, 5}, /* 5.0 MHz */ 90 { 62, 10, 1}, /* 40.0 MHz */ 91 { 62, 12, 3}, /* 20.0 MHz */ 92 { 62, 18, 4}, /* 13.3 MHz */ 93 { 62, 25, 5}, /* 10.0 MHz */ 94 }; 95 96 static const struct scf_period dt_scf_period[] = { 97 { 62, 9, 1}, /* 80.0 MHz */ 98 { 62, 10, 3}, /* 40.0 MHz */ 99 { 62, 12, 5}, /* 20.0 MHz */ 100 { 62, 18, 6}, /* 13.3 MHz */ 101 { 62, 25, 7}, /* 10.0 MHz */ 102 }; 103 #endif 104 105 #define SIOP_SCID 0x04 /* SCSI chip ID R/W */ 106 #define SCID_RRE 0x40 107 #define SCID_SRE 0x20 108 #define SCID_ENCID_SHIFT 0 109 #define SCID_ENCID_MASK 0x07 110 111 #define SIOP_SXFER 0x05 /* SCSI transfer, R/W */ 112 #define SXFER_TP_SHIFT 5 113 #define SXFER_TP_MASK 0xe0 114 #define SXFER_MO_SHIFT 0 115 #define SXFER_MO_MASK 0x3f 116 117 #define SIOP_SDID 0x06 /* SCSI destination ID, R/W */ 118 #define SDID_ENCID_SHIFT 0 119 #define SDID_ENCID_MASK 0x07 120 121 #define SIOP_GPREG 0x07 /* General purpose, R/W */ 122 #define GPREG_GPIO4 0x10 /* 875 only */ 123 #define GPREG_GPIO3 0x08 /* 875 only */ 124 #define GPREG_GPIO2 0x04 /* 875 only */ 125 #define GPREG_GPIO1 0x02 126 #define GPREG_GPIO0 0x01 127 128 #define SIOP_SFBR 0x08 /* SCSI first byte received, R/W */ 129 130 #define SIOP_SOCL 0x09 /* SCSI output control latch, RW */ 131 132 #define SIOP_SSID 0x0A /* SCSI selector ID, RO */ 133 #define SSID_VAL 0x80 134 #define SSID_ENCID_SHIFT 0 135 #define SSID_ENCID_MASK 0x0f 136 137 #define SIOP_SBCL 0x0B /* SCSI control line, RO */ 138 139 #define SIOP_DSTAT 0x0C /* DMA status, RO */ 140 #define DSTAT_DFE 0x80 141 #define DSTAT_MDPE 0x40 142 #define DSTAT_BF 0x20 143 #define DSTAT_ABRT 0x10 144 #define DSTAT_SSI 0x08 145 #define DSTAT_SIR 0x04 146 #define DSTAT_IID 0x01 147 148 #define SIOP_SSTAT0 0x0D /* STSI status 0, RO */ 149 #define SSTAT0_ILF 0x80 150 #define SSTAT0_ORF 0x40 151 #define SSTAT0_OLF 0x20 152 #define SSTAT0_AIP 0x10 153 #define SSTAT0_LOA 0x08 154 #define SSTAT0_WOA 0x04 155 #define SSTAT0_RST 0x02 156 #define SSTAT0_SDP 0x01 157 158 #define SIOP_SSTAT1 0x0E /* STSI status 1, RO */ 159 #define SSTAT1_FFO_SHIFT 4 160 #define SSTAT1_FFO_MASK 0x80 161 #define SSTAT1_SDPL 0x08 162 #define SSTAT1_MSG 0x04 163 #define SSTAT1_CD 0x02 164 #define SSTAT1_IO 0x01 165 #define SSTAT1_PHASE_MASK (SSTAT1_IO | SSTAT1_CD | SSTAT1_MSG) 166 #define SSTAT1_PHASE_DATAOUT 0 167 #define SSTAT1_PHASE_DATAIN SSTAT1_IO 168 #define SSTAT1_PHASE_CMD SSTAT1_CD 169 #define SSTAT1_PHASE_STATUS (SSTAT1_CD | SSTAT1_IO) 170 #define SSTAT1_PHASE_MSGOUT (SSTAT1_MSG | SSTAT1_CD) 171 #define SSTAT1_PHASE_MSGIN (SSTAT1_MSG | SSTAT1_CD | SSTAT1_IO) 172 173 #define SIOP_SSTAT2 0x0F /* STSI status 2, RO */ 174 #define SSTAT2_ILF1 0x80 /* 875 only */ 175 #define SSTAT2_ORF1 0x40 /* 875 only */ 176 #define SSTAT2_OLF1 0x20 /* 875 only */ 177 #define SSTAT2_FF4 0x10 /* 875 only */ 178 #define SSTAT2_SPL1 0x08 /* 875 only */ 179 #define SSTAT2_DF 0x04 /* 875 only */ 180 #define SSTAT2_LDSC 0x02 181 #define SSTAT2_SDP1 0x01 /* 875 only */ 182 183 #define SIOP_DSA 0x10 /* data struct addr, R/W */ 184 185 #define SIOP_ISTAT 0x14 /* IRQ status, R/W */ 186 #define ISTAT_ABRT 0x80 187 #define ISTAT_SRST 0x40 188 #define ISTAT_SIGP 0x20 189 #define ISTAT_SEM 0x10 190 #define ISTAT_CON 0x08 191 #define ISTAT_INTF 0x04 192 #define ISTAT_SIP 0x02 193 #define ISTAT_DIP 0x01 194 195 #define SIOP_CTEST0 0x18 /* Chip test 0, R/W */ 196 #define CTEST0_EHP 0x04 /* 720/770 */ 197 198 #define SIOP_CTEST1 0x19 /* Chip test 1, R/W */ 199 200 #define SIOP_CTEST2 0x1A /* Chip test 2, R/W */ 201 #define CTEST2_SRTCH 0x04 /* 875 only */ 202 203 #define SIOP_CTEST3 0x1B /* Chip test 3, R/W */ 204 #define CTEST3_FLF 0x08 205 #define CTEST3_CLF 0x04 206 #define CTEST3_FM 0x02 207 #define CTEST3_WRIE 0x01 208 209 #define SIOP_TEMP 0x1C /* Temp register (used by CALL/RET), R/W */ 210 211 #define SIOP_DFIFO 0x20 /* DMA FIFO */ 212 213 #define SIOP_CTEST4 0x21 /* Chip test 4, R/W */ 214 #define CTEST4_MUX 0x80 /* 720/770 */ 215 #define CTEST4_BDIS 0x80 216 #define CTEST_ZMOD 0x40 217 #define CTEST_ZSD 0x20 218 #define CTEST_SRTM 0x10 219 #define CTEST_MPEE 0x08 220 221 #define SIOP_CTEST5 0x22 /* Chip test 5, R/W */ 222 #define CTEST5_ADCK 0x80 223 #define CTEST5_BBCK 0x40 224 #define CTEST5_DFS 0x20 225 #define CTEST5_MASR 0x10 226 #define CTEST5_DDIR 0x08 227 #define CTEST5_BOMASK 0x03 228 229 #define SIOP_CTEST6 0x23 /* Chip test 6, R/W */ 230 231 #define SIOP_DBC 0x24 /* DMA byte counter, R/W */ 232 233 #define SIOP_DCMD 0x27 /* DMA command, R/W */ 234 235 #define SIOP_DNAD 0x28 /* DMA next addr, R/W */ 236 237 #define SIOP_DSP 0x2C /* DMA scripts pointer, R/W */ 238 239 #define SIOP_DSPS 0x30 /* DMA scripts pointer save, R/W */ 240 241 #define SIOP_SCRATCHA 0x34 /* scratch register A. R/W */ 242 243 #define SIOP_DMODE 0x38 /* DMA mode, R/W */ 244 #define DMODE_BL_SHIFT 6 245 #define DMODE_BL_MASK 0xC0 246 #define DMODE_SIOM 0x20 247 #define DMODE_DIOM 0x10 248 #define DMODE_ERL 0x08 249 #define DMODE_ERMP 0x04 250 #define DMODE_BOF 0x02 251 #define DMODE_MAN 0x01 252 253 #define SIOP_DIEN 0x39 /* DMA interrupt enable, R/W */ 254 #define DIEN_MDPE 0x40 255 #define DIEN_BF 0x20 256 #define DIEN_AVRT 0x10 257 #define DIEN_SSI 0x08 258 #define DIEN_SIR 0x04 259 #define DIEN_IID 0x01 260 261 #define SIOP_SBR 0x3A /* scratch byte register, R/W */ 262 263 #define SIOP_DCNTL 0x3B /* DMA control, R/W */ 264 #define DCNTL_CLSE 0x80 265 #define DCNTL_PFF 0x40 266 #define DCNTL_EA 0x20 /* 720/770 */ 267 #define DCNTL_PFEN 0x20 /* 8xx */ 268 #define DCNTL_SSM 0x10 269 #define DCNTL_IRQM 0x08 270 #define DCNTL_STD 0x04 271 #define DCNTL_IRQD 0x02 272 #define DCNTL_COM 0x01 273 274 #define SIOP_ADDER 0x3C /* adder output sum, RO */ 275 276 #define SIOP_SIEN0 0x40 /* SCSI interrupt enable 0, R/W */ 277 #define SIEN0_MA 0x80 278 #define SIEN0_CMP 0x40 279 #define SIEN0_SEL 0x20 280 #define SIEN0_RSL 0x10 281 #define SIEN0_SGE 0x08 282 #define SIEN0_UDC 0x04 283 #define SIEN0_SRT 0x02 284 #define SIEN0_PAR 0x01 285 286 #define SIOP_SIEN1 0x41 /* SCSI interrupt enable 1, R/W */ 287 #define SIEN1_SBMC 0x10 /* 895 only */ 288 #define SIEN1_STO 0x04 289 #define SIEN1_GEN 0x02 290 #define SIEN1_HTH 0x01 291 292 #define SIOP_SIST0 0x42 /* SCSI interrupt status 0, RO */ 293 #define SIST0_MA 0x80 294 #define SIST0_CMP 0x40 295 #define SIST0_SEL 0x20 296 #define SIST0_RSL 0x10 297 #define SIST0_SGE 0x08 298 #define SIST0_UDC 0x04 299 #define SIST0_RST 0x02 300 #define SIST0_PAR 0x01 301 302 #define SIOP_SIST1 0x43 /* SCSI interrupt status 1, RO */ 303 #define SIST1_SBMC 0x10 /* 895 only */ 304 #define SIST1_STO 0x04 305 #define SIST1_GEN 0x02 306 #define SIST1_HTH 0x01 307 308 #define SIOP_SLPAR 0x44 /* scsi longitudinal parity, R/W */ 309 310 #define SIOP_SWIDE 0x45 /* scsi wide residue, RW, 875 only */ 311 312 #define SIOP_MACNTL 0x46 /* memory access control, R/W */ 313 314 #define SIOP_GPCNTL 0x47 /* General Purpose Pin control, R/W */ 315 #define GPCNTL_ME 0x80 /* 875 only */ 316 #define GPCNTL_FE 0x40 /* 875 only */ 317 #define GPCNTL_IN4 0x10 /* 875 only */ 318 #define GPCNTL_IN3 0x08 /* 875 only */ 319 #define GPCNTL_IN2 0x04 /* 875 only */ 320 #define GPCNTL_IN1 0x02 321 #define GPCNTL_IN0 0x01 322 323 #define SIOP_STIME0 0x48 /* SCSI timer 0, R/W */ 324 #define STIME0_HTH_SHIFT 4 325 #define STIME0_HTH_MASK 0xf0 326 #define STIME0_SEL_SHIFT 0 327 #define STIME0_SEL_MASK 0x0f 328 329 #define SIOP_STIME1 0x49 /* SCSI timer 1, R/W */ 330 #define STIME1_HTHBA 0x40 /* 875 only */ 331 #define STIME1_GENSF 0x20 /* 875 only */ 332 #define STIME1_HTHSF 0x10 /* 875 only */ 333 #define STIME1_GEN_SHIFT 0 334 #define STIME1_GEN_MASK 0x0f 335 336 #define SIOP_RESPID0 0x4A /* response ID, R/W */ 337 338 #define SIOP_RESPID1 0x4B /* response ID, R/W, 875-only */ 339 340 #define SIOP_STEST0 0x4C /* SCSI test 0, RO */ 341 342 #define SIOP_STEST1 0x4D /* SCSI test 1, RO, RW on 875 */ 343 #define STEST1_DOGE 0x20 /* 1010 only */ 344 #define STEST1_DIGE 0x10 /* 1010 only */ 345 #define STEST1_DBLEN 0x08 /* 875-only */ 346 #define STEST1_DBLSEL 0x04 /* 875-only */ 347 348 #define SIOP_STEST2 0x4E /* SCSI test 2, RO, R/W on 875 */ 349 #define STEST2_DIF 0x20 /* 875 only */ 350 #define STEST2_EXT 0x02 351 352 #define SIOP_STEST3 0x4F /* SCSI test 3, RO, RW on 875 */ 353 #define STEST3_TE 0x80 354 #define STEST3_HSC 0x20 355 356 #define SIOP_STEST4 0x52 /* SCSI test 4, 895 only */ 357 #define STEST4_MODE_MASK 0xc0 358 #define STEST4_MODE_DIF 0x40 359 #define STEST4_MODE_SE 0x80 360 #define STEST4_MODE_LVD 0xc0 361 #define STEST4_LOCK 0x20 362 #define STEST4_ 363 364 #define SIOP_SIDL 0x50 /* SCSI input data latch, RO */ 365 366 #define SIOP_SODL 0x54 /* SCSI output data latch, R/W */ 367 368 #define SIOP_SBDL 0x58 /* SCSI bus data lines, RO */ 369 370 #define SIOP_SCRATCHB 0x5C /* Scratch register B, R/W */ 371 372 #define SIOP_SCRATCHC 0x60 /* Scratch register C, R/W, 875 only */ 373 374 #define SIOP_SCRATCHD 0x64 /* Scratch register D, R/W, 875-only */ 375 376 #define SIOP_SCRATCHE 0x68 /* Scratch register E, R/W, 875-only */ 377 378 #define SIOP_SCRATCHF 0x6c /* Scratch register F, R/W, 875-only */ 379 380 #define SIOP_SCRATCHG 0x70 /* Scratch register G, R/W, 875-only */ 381 382 #define SIOP_SCRATCHH 0x74 /* Scratch register H, R/W, 875-only */ 383 384 #define SIOP_SCRATCHI 0x78 /* Scratch register I, R/W, 875-only */ 385 386 #define SIOP_SCRATCHJ 0x7c /* Scratch register J, R/W, 875-only */ 387 388 #define SIOP_SCNTL4 0xBC /* SCSI control 4, R/W, 1010-only */ 389 #define SCNTL4_XCLKS_ST 0x01 390 #define SCNTL4_XCLKS_DT 0x02 391 #define SCNTL4_XCLKH_ST 0x04 392 #define SCNTL4_XCLKH_DT 0x08 393 #define SCNTL4_AIPEN 0x40 394 #define SCNTL4_U3EN 0x80 395 396 #define SIOP_DFBC 0xf0 /* DMA fifo byte count, RO */ 397 398 #define SIOP_AIPCNTL0 0xbe /* AIP Control 0, 1010-only */ 399 #define AIPCNTL0_ERRLIVE 0x04 /* AIP error status, live */ 400 #define AIPCNTL0_ERR 0x02 /* AIP error status, latched */ 401 #define AIPCNTL0_PARITYERRs 0x01 /* Parity error */ 402 403 #define SIOP_AIPCNTL1 0xbf /* AIP Control 1, 1010-only */ 404 #define AIPCNTL1_DIS 0x08 /* disable AIP generation, 1010-66 only */ 405 #define AIPCNTL1_RSETERR 0x04 /* reset AIP error 1010-66 only */ 406 #define AIPCNTL1_FB 0x02 /* force bad AIP value 1010-66 only */ 407 #define AIPCNTL1_RSET 0x01 /* reset AIP sequence value 1010-66 only */ 408 409 /* 410 * Non-volatile configuration settings stored in the EEPROM. There 411 * are at least two known formats: Symbios Logic format and Tekram format. 412 */ 413 414 #define SIOP_NVRAM_SYM_SIZE 368 415 #define SIOP_NVRAM_SYM_ADDRESS 0x100 416 417 struct nvram_symbios { 418 /* Header (6 bytes) */ 419 u_int16_t type; /* 0x0000 */ 420 u_int16_t byte_count; /* excluding header/trailer */ 421 u_int16_t checksum; 422 423 /* Adapter configuration (20 bytes) */ 424 u_int8_t v_major; 425 u_int8_t v_minor; 426 u_int32_t boot_crc; 427 u_int16_t flags; 428 #define NVRAM_SYM_F_SCAM_ENABLE 0x0001 429 #define NVRAM_SYM_F_PARITY_ENABLE 0x0002 430 #define NVRAM_SYM_F_VERBOSE_MESSAGES 0x0004 431 #define NVRAM_SYM_F_CHS_MAPPING 0x0008 432 u_int16_t flags1; 433 #define NVRAM_SYM_F1_SCAN_HI_LO 0x0001 434 u_int16_t term_state; 435 #define NVRAM_SYM_TERM_CANT_PROGRAM 0 436 #define NVRAM_SYM_TERM_ENABLED 1 437 #define NVRAM_SYM_TERM_DISABLED 2 438 u_int16_t rmvbl_flags; 439 #define NVRAM_SYM_RMVBL_NO_SUPPORT 0 440 #define NVRAM_SYM_RMVBL_BOOT_DEVICE 1 441 #define NVRAM_SYM_RMVBL_MEDIA_INSTALLED 2 442 u_int8_t host_id; 443 u_int8_t num_hba; 444 u_int8_t num_devices; 445 u_int8_t max_scam_devices; 446 u_int8_t num_valid_scam_devices; 447 u_int8_t rsvd; 448 449 /* Boot order (14 bytes x 4) */ 450 struct nvram_symbios_host { 451 u_int16_t type; /* 4 - 8xx */ 452 u_int16_t device_id; /* PCI device ID */ 453 u_int16_t vendor_id; /* PCI vendor ID */ 454 u_int8_t bus_nr; /* PCI bus number */ 455 u_int8_t device_fn; /* PCI device/func # << 3 */ 456 u_int16_t word8; 457 u_int16_t flags; 458 #define NVRAM_SYM_HOST_F_SCAN_AT_BOOT 0x0001 459 u_int16_t io_port; /* PCI I/O address */ 460 } __packed host[4]; 461 462 /* Targets (8 bytes x 16) */ 463 struct nvram_symbios_target { 464 u_int8_t flags; 465 #define NVRAM_SYM_TARG_F_DISCONNECT_EN 0x0001 466 #define NVRAM_SYM_TARG_F_SCAN_AT_BOOT 0x0002 467 #define NVRAM_SYM_TARG_F_SCAN_LUNS 0x0004 468 #define NVRAM_SYM_TARG_F_TQ_EN 0x0008 469 u_int8_t rsvd; 470 u_int8_t bus_width; 471 u_int8_t sync_offset; /* 8, 16, etc. */ 472 u_int16_t sync_period; /* 4 * factor */ 473 u_int16_t timeout; 474 } __packed target[16]; 475 476 /* SCAM table (8 bytes x 4) */ 477 struct nvram_symbios_scam { 478 u_int16_t id; 479 u_int16_t method; 480 #define NVRAM_SYM_SCAM_DEFAULT_METHOD 0 481 #define NVRAM_SYM_SCAM_DONT_ASSIGN 1 482 #define NVRAM_SYM_SCAM_SET_SPECIFIC_ID 2 483 #define NVRAM_SYM_SCAM_USE_ORDER_GIVEN 3 484 u_int16_t status; 485 #define NVRAM_SYM_SCAM_UNKNOWN 0 486 #define NVRAM_SYM_SCAM_DEVICE_NOT_FOUND 1 487 #define NVRAM_SYM_SCAM_ID_NOT_SET 2 488 #define NVRAM_SYM_SCAM_ID_VALID 3 489 u_int8_t target_id; 490 u_int8_t rsvd; 491 } __packed scam[4]; 492 493 u_int8_t spare_devices[15 * 8]; 494 u_int8_t trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */ 495 } __packed; 496 497 #define SIOP_NVRAM_TEK_SIZE 64 498 #define SIOP_NVRAM_TEK_93c46_ADDRESS 0 499 #define SIOP_NVRAM_TEK_24c16_ADDRESS 0x40 500 501 #if 0 502 static const u_int8_t tekram_sync_table[16] __attribute__((__unused__)) = { 503 25, 31, 37, 43, 504 50, 62, 75, 125, 505 12, 15, 18, 21, 506 6, 7, 9, 10, 507 }; 508 509 struct nvram_tekram { 510 struct nvram_tekram_target { 511 u_int8_t flags; 512 #define NVRAM_TEK_TARG_F_PARITY_CHECK 0x01 513 #define NVRAM_TEK_TARG_F_SYNC_NEGO 0x02 514 #define NVRAM_TEK_TARG_F_DISCONNECT_EN 0x04 515 #define NVRAM_TEK_TARG_F_START_CMD 0x08 516 #define NVRAM_TEK_TARG_F_TQ_EN 0x10 517 #define NVRAM_TEK_TARG_F_WIDE_NEGO 0x20 518 u_int8_t sync_index; 519 u_int16_t word2; 520 } __packed target[16]; 521 u_int8_t host_id; 522 u_int8_t flags; 523 #define NVRAM_TEK_F_MORE_THAN_2_DRIVES 0x01 524 #define NVRAM_TEK_F_DRIVES_SUP_1G 0x02 525 #define NVRAM_TEK_F_RESET_ON_POWER_ON 0x04 526 #define NVRAM_TEK_F_ACTIVE_NEGATION 0x08 527 #define NVRAM_TEK_F_IMMEDIATE_SEEK 0x10 528 #define NVRAM_TEK_F_SCAN_LUNS 0x20 529 #define NVRAM_TEK_F_REMOVABLE_FLAGS 0xc0 /* 0 dis, 1 boot, 2 all */ 530 u_int8_t boot_delay_index; 531 u_int8_t max_tags_index; 532 u_int16_t flags1; 533 #define NVRAM_TEK_F_F2_F6_ENABLED 0x0001 534 u_int16_t spare[29]; 535 } __packed; 536 #endif 537