Searched refs:PACKET3_SET_BASE (Results 1 – 18 of 18) sorted by relevance
| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | si_enums.h | 173 #define PACKET3_SET_BASE 0x11 macro
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| H A D | nvd.h | 56 #define PACKET3_SET_BASE 0x11 macro
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| H A D | soc15d.h | 87 #define PACKET3_SET_BASE 0x11 macro
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| H A D | vid.h | 113 #define PACKET3_SET_BASE 0x11 macro
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| H A D | cikd.h | 231 #define PACKET3_SET_BASE 0x11 macro
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| H A D | sid.h | 1666 #define PACKET3_SET_BASE 0x11 macro
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| H A D | gfx_v6_0.c | 2003 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v6_0_cp_gfx_start()
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| H A D | gfx_v7_0.c | 2472 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start()
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| H A D | gfx_v8_0.c | 4194 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v8_0_cp_gfx_start()
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| H A D | gfx_v9_0.c | 3081 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v9_0_cp_gfx_start()
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| H A D | gfx_v10_0.c | 6001 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v10_0_cp_gfx_start()
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| /openbsd/sys/dev/pci/drm/radeon/ |
| H A D | nid.h | 1163 #define PACKET3_SET_BASE 0x11 macro
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| H A D | sid.h | 1603 #define PACKET3_SET_BASE 0x11 macro
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| H A D | cikd.h | 1699 #define PACKET3_SET_BASE 0x11 macro
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| H A D | si.c | 3576 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start()
4461 case PACKET3_SET_BASE: in si_vm_packet3_ce_check()
4539 case PACKET3_SET_BASE: in si_vm_packet3_gfx_check()
4657 case PACKET3_SET_BASE: in si_vm_packet3_compute_check()
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| H A D | evergreen_cs.c | 1996 case PACKET3_SET_BASE: in evergreen_packet3_check()
3358 case PACKET3_SET_BASE: in evergreen_vm_packet3_check()
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| H A D | evergreend.h | 1549 #define PACKET3_SET_BASE 0x11 macro
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| H A D | cik.c | 3990 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
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