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Searched refs:PHYCLKPerState (Results 1 – 11 of 11) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h250 double PHYCLKPerState,
H A Ddisplay_mode_vba_util_32.c1337 double PHYCLKPerState, in dml32_CalculateOutputLink() argument
1378 *OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, in dml32_CalculateOutputLink()
1472 PHYCLKPerState >= 270) { in dml32_CalculateOutputLink()
1478 if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true && in dml32_CalculateOutputLink()
1496 *OutBpp == 0 && PHYCLKPerState >= 540) { in dml32_CalculateOutputLink()
1503 if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true && in dml32_CalculateOutputLink()
1521 …= dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) { in dml32_CalculateOutputLink()
H A Ddisplay_mode_vba_32.c2088 mode_lib->vba.PHYCLKPerState[i], in dml32_ModeSupportAndSystemConfigurationFull()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h603 double PHYCLKPerState[DC__VOLTAGE_STATES]; member
H A Ddisplay_mode_vba.c398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20.c4060 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20_ModeSupportAndSystemConfigurationFull()
4073 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20_ModeSupportAndSystemConfigurationFull()
4102 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20_ModeSupportAndSystemConfigurationFull()
4132 && mode_lib->vba.PHYCLKPerState[i] in dml20_ModeSupportAndSystemConfigurationFull()
H A Ddisplay_mode_vba_20v2.c4174 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20v2_ModeSupportAndSystemConfigurationFull()
4188 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4219 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4251 && mode_lib->vba.PHYCLKPerState[i] in dml20v2_ModeSupportAndSystemConfigurationFull()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c4268 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml21_ModeSupportAndSystemConfigurationFull()
4282 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml21_ModeSupportAndSystemConfigurationFull()
4313 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml21_ModeSupportAndSystemConfigurationFull()
4345 && mode_lib->vba.PHYCLKPerState[i] in dml21_ModeSupportAndSystemConfigurationFull()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c4060 dml_min(600.0, v->PHYCLKPerState[i]) * 10, in dml30_ModeSupportAndSystemConfigurationFull()
4090 if (v->PHYCLKPerState[i] >= 270.0) { in dml30_ModeSupportAndSystemConfigurationFull()
4110 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { in dml30_ModeSupportAndSystemConfigurationFull()
4130 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { in dml30_ModeSupportAndSystemConfigurationFull()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c4307 dml_min(600.0, v->PHYCLKPerState[i]) * 10,
4468 if (v->PHYCLKPerState[i] >= 270.0) {
4488 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
4508 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c4396 dml_min(600.0, v->PHYCLKPerState[i]) * 10,
4557 if (v->PHYCLKPerState[i] >= 270.0) {
4577 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
4597 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {