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Searched refs:REG_WRITE (Results 1 – 25 of 56) sorted by relevance

123

/openbsd/sys/dev/pci/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c102 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
111 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
143 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0); in dmub_dcn30_setup_windows()
144 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0); in dmub_dcn30_setup_windows()
145 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0); in dmub_dcn30_setup_windows()
146 REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0); in dmub_dcn30_setup_windows()
151 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
169 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
179 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
186 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
[all …]
H A Ddmub_dcn20.c139 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn20_reset()
140 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn20_reset()
141 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn20_reset()
142 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn20_reset()
143 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn20_reset()
212 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0); in dmub_dcn20_setup_windows()
213 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0); in dmub_dcn20_setup_windows()
297 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn20_set_inbox1_wptr()
327 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn20_set_outbox1_rptr()
345 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn20_set_outbox0_rptr()
[all …]
H A Ddmub_dcn32.c125 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn32_reset()
126 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn32_reset()
127 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn32_reset()
128 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn32_reset()
129 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); in dmub_dcn32_reset()
130 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); in dmub_dcn32_reset()
131 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn32_reset()
281 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn32_set_inbox1_wptr()
332 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); in dmub_dcn32_set_gpint()
357 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); in dmub_dcn32_get_gpint_dataout()
[all …]
H A Ddmub_dcn31.c131 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn31_reset()
132 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn31_reset()
133 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn31_reset()
134 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn31_reset()
135 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); in dmub_dcn31_reset()
136 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); in dmub_dcn31_reset()
137 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn31_reset()
257 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn31_set_inbox1_wptr()
282 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn31_set_outbox1_rptr()
313 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); in dmub_dcn31_set_gpint()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_hubbub.c404 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg); in hubbub3_init_watermarks()
405 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg); in hubbub3_init_watermarks()
406 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg); in hubbub3_init_watermarks()
409 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg); in hubbub3_init_watermarks()
410 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg); in hubbub3_init_watermarks()
411 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg); in hubbub3_init_watermarks()
414 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg); in hubbub3_init_watermarks()
415 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg); in hubbub3_init_watermarks()
416 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg); in hubbub3_init_watermarks()
429 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg); in hubbub3_init_watermarks()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_abm.c70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); in dce_abm_set_pipe()
115 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); in dmcu_set_backlight_level()
131 REG_WRITE(BIOS_SCRATCH_2, s2); in dmcu_set_backlight_level()
142 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); in dce_abm_init()
143 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); in dce_abm_init()
144 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); in dce_abm_init()
145 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); in dce_abm_init()
146 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); in dce_abm_init()
H A Ddce_panel_cntl.c102 REG_WRITE(BL_PWM_CNTL, in dce_panel_cntl_hw_init()
104 REG_WRITE(BL_PWM_CNTL2, in dce_panel_cntl_hw_init()
106 REG_WRITE(BL_PWM_PERIOD_CNTL, in dce_panel_cntl_hw_init()
125 REG_WRITE(BL_PWM_CNTL, 0x8000FA00); in dce_panel_cntl_hw_init()
126 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); in dce_panel_cntl_hw_init()
133 REG_WRITE(BIOS_SCRATCH_2, value); in dce_panel_cntl_hw_init()
H A Ddce_dmcu.c93 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); in dce_dmcu_load_iram()
96 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); in dce_dmcu_load_iram()
118 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); in dce_get_dmcu_psr_state()
366 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); in dcn10_dmcu_enable_fractional_pwm()
416 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); in dcn10_dmcu_init()
493 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); in dcn10_dmcu_load_iram()
496 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); in dcn10_dmcu_load_iram()
535 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); in dcn10_get_dmcu_psr_state()
842 REG_WRITE(MASTER_COMM_DATA_REG1, header); in dcn10_send_edid_cea()
843 REG_WRITE(MASTER_COMM_DATA_REG2, data1); in dcn10_send_edid_cea()
[all …]
H A Ddce_stream_encoder.c120 REG_WRITE(AFMT_GENERIC_0, *content++); in dce110_update_generic_info_packet()
121 REG_WRITE(AFMT_GENERIC_1, *content++); in dce110_update_generic_info_packet()
122 REG_WRITE(AFMT_GENERIC_2, *content++); in dce110_update_generic_info_packet()
123 REG_WRITE(AFMT_GENERIC_3, *content++); in dce110_update_generic_info_packet()
124 REG_WRITE(AFMT_GENERIC_4, *content++); in dce110_update_generic_info_packet()
125 REG_WRITE(AFMT_GENERIC_5, *content++); in dce110_update_generic_info_packet()
126 REG_WRITE(AFMT_GENERIC_6, *content++); in dce110_update_generic_info_packet()
127 REG_WRITE(AFMT_GENERIC_7, *content); in dce110_update_generic_info_packet()
741 REG_WRITE(AFMT_AVI_INFO0, content[0]); in dce110_stream_encoder_update_hdmi_info_packets()
743 REG_WRITE(AFMT_AVI_INFO1, content[1]); in dce110_stream_encoder_update_hdmi_info_packets()
[all …]
H A Ddmub_abm_lcd.c86 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x3); in dmub_abm_init()
87 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x1); in dmub_abm_init()
88 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x3); in dmub_abm_init()
89 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x1); in dmub_abm_init()
90 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x1); in dmub_abm_init()
H A Ddce_transform.c259 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl); in program_multi_taps_filter()
358 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); in program_scl_ratios_inits()
387 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); in dce60_program_scl_ratios_inits()
423 REG_WRITE(SCL_F_SHARP_CONTROL, 0); in dce_transform_set_scaler()
506 REG_WRITE(SCL_F_SHARP_CONTROL, 0); in dce60_transform_set_scaler()
1455 REG_WRITE(REGAMMA_LUT_INDEX, 0); in program_pwl()
1460 REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); in program_pwl()
1461 REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); in program_pwl()
1462 REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); in program_pwl()
1463 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); in program_pwl()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_hubbub.c803 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg); in hubbub32_init_watermarks()
804 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg); in hubbub32_init_watermarks()
805 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg); in hubbub32_init_watermarks()
808 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg); in hubbub32_init_watermarks()
809 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg); in hubbub32_init_watermarks()
810 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg); in hubbub32_init_watermarks()
813 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg); in hubbub32_init_watermarks()
814 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg); in hubbub32_init_watermarks()
815 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg); in hubbub32_init_watermarks()
828 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg); in hubbub32_init_watermarks()
[all …]
H A Ddcn32_dccg.c219 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg32_set_dtbclk_dto()
220 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); in dccg32_set_dtbclk_dto()
242 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); in dccg32_set_dtbclk_dto()
243 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); in dccg32_set_dtbclk_dto()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c110 REG_WRITE(BL_PWM_CNTL, in dcn301_panel_cntl_hw_init()
112 REG_WRITE(BL_PWM_CNTL2, in dcn301_panel_cntl_hw_init()
114 REG_WRITE(BL_PWM_PERIOD_CNTL, in dcn301_panel_cntl_hw_init()
123 REG_WRITE(BL_PWM_CNTL, 0xC000FA00); in dcn301_panel_cntl_hw_init()
124 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); in dcn301_panel_cntl_hw_init()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c110 REG_WRITE(AFMT_GENERIC_0, *content++); in enc1_update_generic_info_packet()
111 REG_WRITE(AFMT_GENERIC_1, *content++); in enc1_update_generic_info_packet()
112 REG_WRITE(AFMT_GENERIC_2, *content++); in enc1_update_generic_info_packet()
113 REG_WRITE(AFMT_GENERIC_3, *content++); in enc1_update_generic_info_packet()
114 REG_WRITE(AFMT_GENERIC_4, *content++); in enc1_update_generic_info_packet()
115 REG_WRITE(AFMT_GENERIC_5, *content++); in enc1_update_generic_info_packet()
116 REG_WRITE(AFMT_GENERIC_6, *content++); in enc1_update_generic_info_packet()
117 REG_WRITE(AFMT_GENERIC_7, *content); in enc1_update_generic_info_packet()
839 REG_WRITE(AFMT_GENERIC_0, *content++); in enc1_stream_encoder_send_immediate_sdp_message()
840 REG_WRITE(AFMT_GENERIC_1, *content++); in enc1_stream_encoder_send_immediate_sdp_message()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_opp.c268 REG_WRITE(DPG_CONTROL, 0); in opp2_set_disp_pattern_generator()
269 REG_WRITE(DPG_COLOUR_R_CR, 0); in opp2_set_disp_pattern_generator()
270 REG_WRITE(DPG_COLOUR_G_Y, 0); in opp2_set_disp_pattern_generator()
271 REG_WRITE(DPG_COLOUR_B_CB, 0); in opp2_set_disp_pattern_generator()
272 REG_WRITE(DPG_RAMP_CONTROL, 0); in opp2_set_disp_pattern_generator()
H A Ddcn20_stream_encoder.c260 REG_WRITE(AFMT_GENERIC_0, *content++); in enc2_update_gsp7_128_info_packet()
261 REG_WRITE(AFMT_GENERIC_1, *content++); in enc2_update_gsp7_128_info_packet()
262 REG_WRITE(AFMT_GENERIC_2, *content++); in enc2_update_gsp7_128_info_packet()
263 REG_WRITE(AFMT_GENERIC_3, *content++); in enc2_update_gsp7_128_info_packet()
264 REG_WRITE(AFMT_GENERIC_4, *content++); in enc2_update_gsp7_128_info_packet()
265 REG_WRITE(AFMT_GENERIC_5, *content++); in enc2_update_gsp7_128_info_packet()
266 REG_WRITE(AFMT_GENERIC_6, *content++); in enc2_update_gsp7_128_info_packet()
267 REG_WRITE(AFMT_GENERIC_7, *content++); in enc2_update_gsp7_128_info_packet()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_vbios_smu.c110 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in rv1_vbios_smu_send_msg_with_param()
113 REG_WRITE(MP1_SMN_C2PMSG_83, param); in rv1_vbios_smu_send_msg_with_param()
116 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in rv1_vbios_smu_send_msg_with_param()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr_smu_msg.c74 REG_WRITE(DAL_RESP_REG, 0); in dcn32_smu_send_msg_with_param()
77 REG_WRITE(DAL_ARG_REG, param_in); in dcn32_smu_send_msg_with_param()
80 REG_WRITE(DAL_MSG_REG, msg_id); in dcn32_smu_send_msg_with_param()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c120 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in dcn31_smu_send_msg_with_param()
123 REG_WRITE(MP1_SMN_C2PMSG_83, param); in dcn31_smu_send_msg_with_param()
126 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn31_smu_send_msg_with_param()
136 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK); in dcn31_smu_send_msg_with_param()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.c583 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg31_set_dtbclk_dto()
584 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); in dccg31_set_dtbclk_dto()
605 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); in dccg31_set_dtbclk_dto()
606 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); in dccg31_set_dtbclk_dto()
625 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo); in dccg31_set_audio_dtbclk_dto()
626 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase); in dccg31_set_audio_dtbclk_dto()
634 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0); in dccg31_set_audio_dtbclk_dto()
635 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0); in dccg31_set_audio_dtbclk_dto()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c135 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in dcn314_smu_send_msg_with_param()
138 REG_WRITE(MP1_SMN_C2PMSG_83, param); in dcn314_smu_send_msg_with_param()
141 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn314_smu_send_msg_with_param()
154 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK); in dcn314_smu_send_msg_with_param()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr_vbios_smu.c113 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in rn_vbios_smu_send_msg_with_param()
116 REG_WRITE(MP1_SMN_C2PMSG_83, param); in rn_vbios_smu_send_msg_with_param()
119 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in rn_vbios_smu_send_msg_with_param()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c113 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in dcn301_smu_send_msg_with_param()
116 REG_WRITE(MP1_SMN_C2PMSG_83, param); in dcn301_smu_send_msg_with_param()
119 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn301_smu_send_msg_with_param()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr_smu_msg.c84 REG_WRITE(DAL_RESP_REG, 0); in dcn30_smu_send_msg_with_param()
87 REG_WRITE(DAL_ARG_REG, param_in); in dcn30_smu_send_msg_with_param()
90 REG_WRITE(DAL_MSG_REG, msg_id); in dcn30_smu_send_msg_with_param()

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