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Searched refs:RegClasses (Results 1 – 4 of 4) sorted by relevance

/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp981 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { in computeSubClasses()
1006 for (auto &RC : RegClasses) { in computeSubClasses()
1022 for (auto &RC : RegClasses) in computeSubClasses()
1050 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs()
1060 for (auto &RC: RegClasses) { in getMatchingSubClassWithSubRegs()
1261 for (auto &RC : RegClasses) in CodeGenRegBank()
1326 return &RegClasses.back(); in getOrCreateSubClass()
2201 assert(!RegClasses.empty()); in inferCommonSubClass()
2204 for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end()); in inferCommonSubClass()
2356 assert(!RegClasses.empty()); in computeInferredRegisterClasses()
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H A DCodeGenRegisters.h582 std::list<CodeGenRegisterClass> RegClasses; variable
627 inferMatchingSuperRegClass(RC, RegClasses.begin()); in inferMatchingSuperRegClass()
748 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses()
751 return RegClasses; in getRegClasses()
H A DCodeGenTarget.cpp313 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace() local
314 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; in getRegNamespace()
376 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg() local
380 for (CodeGenRegisterClass &RC : RegClasses) { in getSuperRegForSubReg()
/openbsd/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSchedule.td479 // a list of register classes (see field `RegClasses`). An empty list of
483 // A register R can be renamed if its register class appears in the `RegClasses`
488 // However, V is only renamed if its register class is part of `RegClasses`.
499 // register class that is in `RegClasses`.
541 list<RegisterClass> RegClasses = Classes;