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/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h104 IndexedMap<std::pair<Register, SmallVector<Register, 4>>,
181 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) { in noteCloneVirtualRegister()
625 void replaceRegWith(Register FromReg, Register ToReg);
736 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
755 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
801 void addRegAllocationHint(Register VReg, Register PrefReg) { in addRegAllocationHint()
808 void setSimpleHint(Register VReg, Register PrefReg) { in setSimpleHint()
821 std::pair<Register, Register>
832 Register getSimpleHint(Register VReg) const { in getSimpleHint()
840 const std::pair<Register, SmallVector<Register, 4>>
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H A DVirtRegMap.h99 bool hasPhys(Register virtReg) const { in hasPhys()
105 MCRegister getPhys(Register virtReg) const { in getPhys()
116 bool hasShape(Register virtReg) const { in hasShape()
120 ShapeT getShape(Register virtReg) const { in getShape()
131 void clearVirt(Register virtReg) { in clearVirt()
153 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg()
161 Register getPreSplitReg(Register virtReg) const { in getPreSplitReg()
169 Register getOriginal(Register VirtReg) const { in getOriginal()
170 Register Orig = getPreSplitReg(VirtReg); in getOriginal()
187 int getStackSlot(Register virtReg) const { in getStackSlot()
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H A DFunctionLoweringInfo.h69 Register DemoteRegister;
77 DenseMap<const Value *, Register> ValueMap;
84 DenseMap<Register, const Value*> VirtReg2Value;
88 const Value *getValueFromVirtualReg(Register Vreg);
114 Register Reg;
142 DenseMap<Register, Register> RegFixups;
144 DenseSet<Register> RegsWithFixups;
204 Register CreateRegs(const Value *V);
208 Register InitializeRegForValue(const Value *V) { in InitializeRegForValue()
212 Register &R = ValueMap[V]; in InitializeRegForValue()
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H A DLiveVariables.h109 bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
152 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
157 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
158 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
164 MachineInstr *FindLastRefOrPartRef(Register Reg);
169 MachineInstr *FindLastPartialDef(Register Reg,
196 void recomputeForSingleDefVirtReg(Register Reg);
277 VarInfo &getVarInfo(Register Reg);
285 void HandleVirtRegDef(Register reg, MachineInstr &MI);
288 bool isLiveIn(Register Reg, const MachineBasicBlock &MBB) { in isLiveIn()
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H A DRegister.h19 class Register {
23 constexpr Register(unsigned Val = 0): Reg(Val) {} in Reg()
24 constexpr Register(MCRegister Val): Reg(Val) {} in Register() function
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index()
58 static Register index2StackSlot(int FI) { in index2StackSlot()
60 return Register(FI + MCRegister::FirstStackSlot); in index2StackSlot()
77 static unsigned virtReg2Index(Register Reg) { in virtReg2Index()
84 static Register index2VirtReg(unsigned Index) { in index2VirtReg()
148 template<> struct DenseMapInfo<Register> {
155 static unsigned getHashValue(const Register &Val) {
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H A DLiveRangeEdit.h56 virtual bool LRE_CanEraseVirtReg(Register) { return true; } in LRE_CanEraseVirtReg() argument
59 virtual void LRE_WillShrinkVirtReg(Register) {} in LRE_WillShrinkVirtReg() argument
63 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} in LRE_DidCloneVirtReg()
68 SmallVectorImpl<Register> &NewRegs;
108 void MRI_NoteNewVirtualRegister(Register VReg) override;
146 Register getReg() const { return getParent().reg(); } in getReg()
149 using iterator = SmallVectorImpl<Register>::const_iterator;
154 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } in get()
169 Register createFrom(Register OldReg);
177 Register create() { return createFrom(getReg()); } in create()
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/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h56 Register Addr;
57 Register Base;
58 Register Offset;
64 Register Base;
69 Register Reg;
85 Register WideSrcVal;
494 std::tuple<Register, Register> &MatchInfo);
496 std::tuple<Register, Register> &MatchInfo);
544 std::pair<Register, Register> &MatchInfo);
854 computeRetValAgainstNaN(Register LHS, Register RHS,
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H A DUtils.h145 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
180 Register VReg;
186 getIConstantVRegValWithLookThrough(Register VReg,
193 Register VReg, const MachineRegisterInfo &MRI,
198 Register VReg;
204 getFConstantVRegValWithLookThrough(Register VReg,
221 Register Reg;
235 MachineInstr *getDefIgnoringCopies(Register Reg,
244 Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
354 Register Reg;
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H A DCallLowering.h118 Register SwiftErrorVReg;
143 Register DemoteRegister;
268 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
274 virtual void assignValueToAddress(Register ValVReg, Register Addr,
305 copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
312 Register extendRegister(Register ValReg, CCValAssign &VA,
324 Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
327 void assignValueToReg(Register ValVReg, Register PhysReg,
451 ArrayRef<Register> VRegs, Register DemoteReg,
457 ArrayRef<Register> VRegs, Register DemoteReg) const;
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H A DLegalizerHelper.h127 Register coerceToScalar(Register Val);
211 void insertParts(Register DstReg, LLT ResultTy,
216 void mergeMixedSubvectors(Register DstReg, ArrayRef<Register> PartRegs);
218 void appendVectorElts(SmallVectorImpl<Register> &Elts, Register Reg);
225 LLT NarrowTy, Register SrcReg);
231 Register SrcReg);
272 LegalizeResult lowerMemset(MachineInstr &MI, Register Dst, Register Val,
275 LegalizeResult lowerMemcpyInline(MachineInstr &MI, Register Dst, Register Src,
278 LegalizeResult lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
281 LegalizeResult lowerMemmove(MachineInstr &MI, Register Dst, Register Src,
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H A DGISelKnownBits.h36 SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
63 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
66 KnownBits getKnownBits(Register R);
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
72 APInt getKnownZeroes(Register R);
73 APInt getKnownOnes(Register R);
78 bool maskedValueIsZero(Register Val, const APInt &Mask) { in maskedValueIsZero()
84 bool signBitIsZero(Register Op);
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H A DLegalizationArtifactCombiner.h67 Register TruncSrc; in tryCombineAnyExt()
81 Register ExtSrc; in tryCombineAnyExt()
122 Register TruncSrc; in tryCombineZExt()
123 Register SextSrc; in tryCombineZExt()
145 Register ZextSrc; in tryCombineZExt()
200 Register ExtSrc; in tryCombineSExt()
516 static void replaceRegOrBuildCopy(Register DstReg, Register SrcReg, in replaceRegOrBuildCopy()
562 Register CurrentBest = Register();
725 Register findValueFromDefImpl(Register DefReg, unsigned StartBit, in findValueFromDefImpl()
776 Register findValueFromDef(Register DefReg, unsigned StartBit, in findValueFromDef()
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/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h48 Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap);
54 DenseMap<SDValue, Register> &VRBaseMap);
58 Register getVR(SDValue Op,
59 DenseMap<SDValue, Register> &VRBaseMap);
68 DenseMap<SDValue, Register> &VRBaseMap,
79 DenseMap<SDValue, Register> &VRBaseMap,
85 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
118 DenseMap<SDValue, Register> &VRBaseMap);
143 DenseMap<SDValue, Register> &VRBaseMap) { in EmitNode()
163 DenseMap<SDValue, Register> &VRBaseMap);
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/openbsd/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h87 Register find(const Constant *C, MachineFunction *MF) { in find()
95 Register find(const Function *F, MachineFunction *MF) { in find()
106 SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
119 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
146 SPIRVType *getSPIRVTypeForVReg(Register VReg) const;
149 bool hasSPIRVTypeForVReg(Register VReg) const { in hasSPIRVTypeForVReg()
154 Register getSPIRVTypeID(const SPIRVType *SpirvType) const;
203 Register Reg);
225 Register getOrCreateIntCompositeOrNull(uint64_t Val,
250 Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param,
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/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp63 void MachineSSAUpdater::Initialize(Register V) { in Initialize()
89 return Register(); in LookForIdenticalPHI()
93 return Register(); in LookForIdenticalPHI()
112 return Register(); in LookForIdenticalPHI()
159 return Register(); in GetValueInMiddleOfBlock()
170 Register SingularValue; in GetValueInMiddleOfBlock()
182 SingularValue = Register(); in GetValueInMiddleOfBlock()
196 return Register(); in GetValueInMiddleOfBlock()
236 Register NewVR; in RewriteUse()
255 using ValT = Register;
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H A DRegAllocGreedy.h92 void setStage(Register Reg, LiveRangeStage Stage) { in setStage()
103 LiveRangeStage getOrInitStage(Register Reg) { in getOrInitStage()
110 void setCascade(Register Reg, unsigned Cascade) { in setCascade()
115 unsigned getOrAssignNewCascade(Register Reg) { in getOrAssignNewCascade()
134 Register Reg = *Begin; in setStage()
140 void LRE_DidCloneVirtReg(Register New, Register Old);
321 bool LRE_CanEraseVirtReg(Register) override;
322 void LRE_WillShrinkVirtReg(Register) override;
323 void LRE_DidCloneVirtReg(Register, Register) override;
388 Register Reg;
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H A DMachineRegisterInfo.cpp62 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
91 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
146 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister()
156 Register
170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister()
184 Register
201 Register Reg = Register::index2VirtReg(i); in clearVirtRegs()
258 verifyUseList(Register::index2VirtReg(i)); in verifyUseLists()
380 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) { in replaceRegWith()
462 return Register(); in getLiveInVirtReg()
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H A DTwoAddressInstructionPass.cpp112 DenseMap<Register, Register> SrcRegMap;
117 DenseMap<Register, Register> DstRegMap;
121 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
125 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131 bool isProfitableToConv3Addr(Register RegA, Register RegB);
394 Register SrcReg; in findOnlyInterestingUse()
425 DenseMap<Register, Register>::iterator SI = RegMap.find(Reg); in getMappedReg()
436 static bool regsAreCompatible(Register RegA, Register RegB, in regsAreCompatible()
447 DenseMap<Register, Register> &RegMap, in removeMapRegEntry() argument
681 Register RegA, Register RegB, unsigned &Dist) { in convertInstTo3Addr()
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h40 Register getSegmentAperture(unsigned AddrSpace,
91 ArrayRef<Register> Src0, ArrayRef<Register> Src1,
98 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
101 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
120 Register DstRemReg, Register Num,
121 Register Den) const;
124 Register DstRemReg, Register Num,
125 Register Den) const;
157 bool getLDSKernelId(Register DstReg, MachineRegisterInfo &MRI,
169 Register SOffset, unsigned ImmOffset, Register VIndex,
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H A DSIMachineFunctionInfo.h344 Register Reg;
482 SmallVector<Register, 2> SpillVGPRs;
520 Register VGPRForAGPRCopy;
586 Register getScratchSGPRCopyDstReg(Register Reg) const {
686 Register addLDSKernelId();
689 Register addReservedUserSGPR() {
690 Register Next = getNextUserSGPR();
696 Register addWorkGroupIDX() {
702 Register addWorkGroupIDY() {
708 Register addWorkGroupIDZ() {
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H A DAMDGPUInstructionSelector.h71 bool isSGPR(Register Reg) const;
149 std::pair<Register, unsigned>
153 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
176 std::pair<Register, unsigned>
200 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
226 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
240 std::pair<Register, unsigned>
256 std::pair<Register, int64_t>
257 getPtrBaseWithConstantOffset(Register Root,
264 Register N0, N2, N3;
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H A DAMDGPURegisterBankInfo.h48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
51 SmallSet<Register, 4> &SGPROperandRegs,
59 SmallSet<Register, 4> &SGPROperandRegs,
63 Register Src) const;
92 Register Reg) const;
94 std::pair<Register, unsigned>
101 Register Ptr) const;
110 const ValueMapping *getSGPROpMapping(Register Reg,
115 const ValueMapping *getVGPROpMapping(Register Reg,
120 const ValueMapping *getAGPROpMapping(Register Reg,
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp38 void assignValueToReg(Register ValVReg, Register PhysReg,
40 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
42 Register getStackAddress(uint64_t Size, int64_t Offset,
50 void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
53 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
57 void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr, in assignValueToAddress()
76 Register SwiftErrorVReg) const { in lowerReturn()
144 void PPCIncomingValueHandler::assignValueToReg(Register ValVReg, in assignValueToReg()
145 Register PhysReg, in assignValueToReg()
151 void PPCIncomingValueHandler::assignValueToAddress(Register ValVReg, in assignValueToAddress()
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/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp69 const Register ReservedRegs[] = { in getReservedRegs()
136 Register clobber;
243 Register SrcReg = MI.getOperand(3).getReg(); in processSTQ()
264 Register DestReg = MI.getOperand(0).getReg(); in processLDQ()
296 Register SrcReg = MI.getOperand(3).getReg(); in processSTVM()
300 Register TmpReg = VE::SX16; in processSTVM()
334 Register DestReg = MI.getOperand(0).getReg(); in processLDVM()
374 Register SrcReg = MI.getOperand(3).getReg(); in processSTVM512()
380 Register TmpReg = VE::SX16; in processSTVM512()
425 Register TmpReg = VE::SX16; in processLDVM512()
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/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp77 static Register buildLogBase2(Register V, MachineIRBuilder &MIB) { in buildLogBase2()
1655 Register ExtSrc; in matchCombineShlOfExtend()
1719 static Register peekThroughBitcast(Register Reg, in peekThroughBitcast()
2824 Register Src; in matchAshrShlToSextInreg()
2841 Register Src; in applyAshShlToSextInreg()
2858 Register R; in matchOverlappingAnd()
3125 Register X, Y; in applyXorOfAndWithSameReg()
4317 Register Src; in matchAndOrDisjointMask()
5479 Register Z; in matchCombineFAddFMAFMulToFMadOrFMA()
5548 auto buildMatchInfo = [=, &MI](Register U, Register V, Register Z, Register X, in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
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