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Searched refs:S12 (Results 1 – 17 of 17) sorted by relevance

/openbsd/lib/libm/src/ld128/
H A Dk_sinl.c44 S12 = 0.64038150078671872796678569586315881020659912139412e-25; variable
54 z*(S9+z*(S10+z*(S11+z*S12))))))))); in __kernel_sinl()
H A Dk_sincosl.h40 S12 = 0.64038150078671872796678569586315881020659912139412e-25; variable
55 z * (S9 + z * (S10 + z * (S11 + z * S12))))))))); in __kernel_sincosl()
/openbsd/gnu/usr.bin/binutils/opcodes/
H A Dfrv-opc.c1784 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1790 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1796 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1802 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1808 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1814 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1820 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1826 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1832 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
3866 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } },
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/opcodes/
H A Dfrv-opc.c1882 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1888 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1894 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1900 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1906 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1912 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1918 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1924 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
1930 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
3904 { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } },
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARC/
H A DARCInstrFormats.td381 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
386 bits<12> S12;
394 let Inst{11-6} = S12{5-0};
395 let Inst{5-0} = S12{11-6};
401 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
406 bits<12> S12;
414 let Inst{11-6} = S12{5-0};
415 let Inst{5-0} = S12{11-6};
H A DARCInstrInfo.td214 (ins GPR32:$in, immS<12>:$S12),
215 !strconcat(opasm, "\t$B, $in, $S12"),
220 (ins GPR32:$in, immS<12>:$S12),
221 !strconcat(opasm, ".f\t$B, $in, $S12"),
369 (outs GPR32:$B), (ins immS<12>:$S12),
370 "mov\t$B, $S12",
371 [(set GPR32:$B, immS<12>:$S12)]>;
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMCallingConv.td80 S9, S10, S11, S12, S13, S14, S15]>>,
100 S9, S10, S11, S12, S13, S14, S15]>>,
228 S9, S10, S11, S12, S13, S14, S15]>>,
248 S9, S10, S11, S12, S13, S14, S15]>>,
H A DARMCallingConv.cpp158 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
H A DARMRegisterInfo.td108 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
127 def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
/openbsd/etc/
H A Dpf.os397 S12:64:1:48:M*,N,N,S: Windows:98::Windows 98
432 S12:128:1:48:M*,N,N,S: Windows:XP:SP1:Windows XP SP1
571 S12:64:1:44:M1460: @Checkpoint:::Checkpoint (unknown 1)
572 S12:64:1:48:N,N,S,M1460: @Checkpoint:::Checkpoint (unknown 2)
652 S12:64:0:44:M1452: AXIS:5600:v5.64:AXIS Printer Server 5600 v5.64
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp102 case AArch64::S12: in isOdd()
H A DAArch64RegisterInfo.td346 def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>;
381 def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td301 def S12 : Rs<12, "s12">, DwarfRegNum<[156]>;
380 def S13_12 : Rss<12, "s13:12", [S12, S13]>, DwarfRegNum<[156]>;
600 S11, S12, S13, S14, S15,
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp150 {codeview::RegisterId::ARM64_S12, AArch64::S12}, in initLLVMToCVRegMapping()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp261 {codeview::RegisterId::ARM_FS12, ARM::S12}, in initLLVMToCVRegMapping()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp782 Hexagon::S12, Hexagon::S13, Hexagon::S14,
/openbsd/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1493 ARM::S12, ARM::S13, ARM::S14, ARM::S15,