| /openbsd/usr.bin/file/magdir/ |
| H A D | archive | 398 # SBC
399 0 string SBC SBC archive data
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| /openbsd/sys/arch/hppa/hppa/ |
| H A D | db_disasm.c | 185 #define SBC 0xC macro
1496 case SBC: return(",sbc");
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedTSV110.td | 373 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>;
374 def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(ADC|SBC)S[WX]r$")>;
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| H A D | AArch64SchedAmpere1.td | 937 (instregex "ADC(W|X)r", "SBC(W|X)r")>;
943 (instregex "(ADC|SBC)S(W|X)r")>;
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| H A D | AArch64SchedExynosM5.td | 635 def : InstRW<[M5WriteA1W], (instregex "^(ADC|SBC)S?Wr$")>;
636 def : InstRW<[M5WriteA1X], (instregex "^(ADC|SBC)S?Xr$")>;
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| H A D | AArch64SchedThunderX2T99.td | 432 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
454 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
473 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
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| H A D | AArch64SchedThunderX3T110.td | 692 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
714 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
733 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
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| H A D | AArch64ISelLowering.h | 91 SBC, // adc, sbc instructions enumerator
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| H A D | AArch64SchedA64FX.td | 609 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
629 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
646 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
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| H A D | AArch64SchedCyclone.td | 144 // ADC(S),SBC(S)
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| H A D | AArch64SchedFalkorDetails.td | 902 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SBC(S)?(W|X)r$")>;
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| H A D | AArch64ISelLowering.cpp | 2350 MAKE_CASE(AArch64ISD::SBC) in getTargetNodeName()
21411 case AArch64ISD::SBC: in PerformDAGCombine()
21420 return performFlagSettingCombine(N, DCI, AArch64ISD::SBC); in PerformDAGCombine()
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| H A D | AArch64InstrInfo.td | 612 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
1762 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
|
| /openbsd/gnu/llvm/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 2284 auto SBC = in expand() local
2291 SBC->getOperand(3).setIsDead(); in expand()
2294 SBC->getOperand(4).setIsKill(); in expand()
|
| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 326 (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
|
| H A D | ARMScheduleSwift.td | 129 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
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| H A D | ARMScheduleA57.td | 171 // RSB{S}, RSC{S}, SUB{S}, SBC{S}, TEQ, TST
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| H A D | ARMInstrThumb2.td | 4851 // Aliases for SBC without the ".w" optional width specifier.
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| H A D | ARMInstrInfo.td | 3867 defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>;
|
| /openbsd/gnu/llvm/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.td | 312 defm SBC : ArcBinaryGEN4Inst<0b000011, "sbc">;
|
| /openbsd/gnu/usr.bin/binutils/gas/ |
| H A D | ChangeLog-9295 | 2728 (OPCODE_{AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,TST,TEQ,CMP,CMN,ORR,MOV,BIC,
|
| /openbsd/gnu/usr.bin/binutils-2.17/gas/ |
| H A D | ChangeLog-9295 | 2728 (OPCODE_{AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,TST,TEQ,CMP,CMN,ORR,MOV,BIC,
|