1 /* $OpenBSD: if_bwfm_sdio.h,v 1.3 2020/03/06 09:28:40 patrick Exp $ */ 2 /* 3 * Copyright (c) 2010-2016 Broadcom Corporation 4 * Copyright (c) 2018 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Registers */ 20 #define BWFM_SDIO_CCCR_CARDCAP 0xf0 21 #define BWFM_SDIO_CCCR_CARDCAP_CMD14_SUPPORT (1 << 1) 22 #define BWFM_SDIO_CCCR_CARDCAP_CMD14_EXT (1 << 2) 23 #define BWFM_SDIO_CCCR_CARDCAP_CMD_NODEC (1 << 3) 24 #define BWFM_SDIO_CCCR_CARDCTRL 0xf1 25 #define BWFM_SDIO_CCCR_CARDCTRL_WLANRESET (1 << 1) 26 #define BWFM_SDIO_CCCR_SEPINT 0xf2 27 #define BWFM_SDIO_CCCR_SEPINT_MASK 0x01 28 #define BWFM_SDIO_CCCR_SEPINT_OE (1 << 1) 29 #define BWFM_SDIO_CCCR_SEPINT_ACT_HI (1 << 2) 30 31 #define BWFM_SDIO_WATERMARK 0x10008 32 #define BWFM_SDIO_DEVICE_CTL 0x10009 33 #define BWFM_SDIO_DEVICE_CTL_SETBUSY 0x01 34 #define BWFM_SDIO_DEVICE_CTL_SPI_INTR_SYNC 0x02 35 #define BWFM_SDIO_DEVICE_CTL_CA_INT_ONLY 0x04 36 #define BWFM_SDIO_DEVICE_CTL_PADS_ISO 0x08 37 #define BWFM_SDIO_DEVICE_CTL_SB_RST_CTL 0x30 38 #define BWFM_SDIO_DEVICE_CTL_RST_CORECTL 0x00 39 #define BWFM_SDIO_DEVICE_CTL_RST_BPRESET 0x10 40 #define BWFM_SDIO_DEVICE_CTL_RST_NOBPRESET 0x20 41 #define BWFM_SDIO_FUNC1_SBADDRLOW 0x1000A 42 #define BWFM_SDIO_FUNC1_SBADDRMID 0x1000B 43 #define BWFM_SDIO_FUNC1_SBADDRHIGH 0x1000C 44 #define BWFM_SDIO_FUNC1_CHIPCLKCSR 0x1000E 45 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_ALP 0x01 46 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_HT 0x02 47 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_ILP 0x04 48 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL_REQ 0x08 49 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL_REQ 0x10 50 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_HW_CLKREQ_OFF 0x20 51 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL 0x40 52 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL 0x80 53 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_CSR_MASK 0x1F 54 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS \ 55 (BWFM_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL | \ 56 BWFM_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL) 57 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) \ 58 ((regval) & BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS) 59 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval) \ 60 (((regval) & BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS) == BWFM_SDIO_FUNC1_CHIPCLKCSR_AVBITS) 61 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPONLY(regval) \ 62 (BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) && \ 63 !BWFM_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval)) 64 #define BWFM_SDIO_FUNC1_CHIPCLKCSR_CLKAV(regval, alponly) \ 65 (BWFM_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) && \ 66 (alponly ? 1 : BWFM_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval))) 67 #define BWFM_SDIO_FUNC1_SDIOPULLUP 0x1000F 68 #define BWFM_SDIO_FUNC1_WAKEUPCTRL 0x1001E 69 #define BWFM_SDIO_FUNC1_WAKEUPCTRL_HTWAIT (1 << 1) 70 #define BWFM_SDIO_FUNC1_SLEEPCSR 0x1001F 71 #define BWFM_SDIO_FUNC1_SLEEPCSR_KSO (1 << 0) 72 #define BWFM_SDIO_FUNC1_SLEEPCSR_DEVON (1 << 1) 73 74 #define BWFM_SDIO_SB_OFT_ADDR_PAGE 0x08000 75 #define BWFM_SDIO_SB_OFT_ADDR_MASK 0x07FFF 76 #define BWFM_SDIO_SB_ACCESS_2_4B_FLAG 0x08000 77 78 /* Protocol defines */ 79 #define SDPCM_PROT_VERSION 4 80 #define SDPCM_PROT_VERSION_SHIFT 16 81 #define SDPCM_SHARED_VERSION 0x0003 82 #define SDPCM_SHARED_VERSION_MASK 0x00FF 83 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 84 #define SDPCM_SHARED_ASSERT 0x0200 85 #define SDPCM_SHARED_TRAP 0x0400 86 87 #define SDPCMD_INTSTATUS 0x020 88 #define SDPCMD_INTSTATUS_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 89 #define SDPCMD_INTSTATUS_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 90 #define SDPCMD_INTSTATUS_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 91 #define SDPCMD_INTSTATUS_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 92 #define SDPCMD_INTSTATUS_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 93 #define SDPCMD_INTSTATUS_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 94 #define SDPCMD_INTSTATUS_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 95 #define SDPCMD_INTSTATUS_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 96 #define SDPCMD_INTSTATUS_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 97 #define SDPCMD_INTSTATUS_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 98 #define SDPCMD_INTSTATUS_HMB_FC_STATE SDPCMD_INTSTATUS_HMB_SW0 99 #define SDPCMD_INTSTATUS_HMB_FC_CHANGE SDPCMD_INTSTATUS_HMB_SW1 100 #define SDPCMD_INTSTATUS_HMB_FRAME_IND SDPCMD_INTSTATUS_HMB_SW2 101 #define SDPCMD_INTSTATUS_HMB_HOST_INT SDPCMD_INTSTATUS_HMB_SW3 102 #define SDPCMD_INTSTATUS_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 103 #define SDPCMD_INTSTATUS_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 104 #define SDPCMD_INTSTATUS_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 105 #define SDPCMD_INTSTATUS_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 106 #define SDPCMD_INTSTATUS_PC (1 << 10)/* descriptor error */ 107 #define SDPCMD_INTSTATUS_PD (1 << 11)/* data error */ 108 #define SDPCMD_INTSTATUS_DE (1 << 12)/* Descriptor protocol Error */ 109 #define SDPCMD_INTSTATUS_RU (1 << 13)/* Receive descriptor Underflow */ 110 #define SDPCMD_INTSTATUS_RO (1 << 14)/* Receive fifo Overflow */ 111 #define SDPCMD_INTSTATUS_XU (1 << 15)/* Transmit fifo Underflow */ 112 #define SDPCMD_INTSTATUS_RI (1 << 16)/* Receive Interrupt */ 113 #define SDPCMD_INTSTATUS_BUSPWR (1 << 17)/* SDIO Bus Power Change (rev 9) */ 114 #define SDPCMD_INTSTATUS_XMTDATA_AVAIL (1 << 23)/* bits in fifo */ 115 #define SDPCMD_INTSTATUS_XI (1 << 24)/* Transmit Interrupt */ 116 #define SDPCMD_INTSTATUS_RF_TERM (1 << 25)/* Read Frame Terminate */ 117 #define SDPCMD_INTSTATUS_WF_TERM (1 << 26)/* Write Frame Terminate */ 118 #define SDPCMD_INTSTATUS_PCMCIA_XU (1 << 27)/* PCMCIA Transmit FIFO Underflow */ 119 #define SDPCMD_INTSTATUS_SBINT (1 << 28)/* sbintstatus Interrupt */ 120 #define SDPCMD_INTSTATUS_CHIPACTIVE (1 << 29)/* chip from doze to active state */ 121 #define SDPCMD_INTSTATUS_SRESET (1 << 30)/* CCCR RES interrupt */ 122 #define SDPCMD_INTSTATUS_IOE2 (1U << 31)/* CCCR IOE2 Bit Changed */ 123 #define SDPCMD_INTSTATUS_ERRORS (SDPCMD_INTSTATUS_PC | \ 124 SDPCMD_INTSTATUS_PD | \ 125 SDPCMD_INTSTATUS_DE | \ 126 SDPCMD_INTSTATUS_RU | \ 127 SDPCMD_INTSTATUS_RO | \ 128 SDPCMD_INTSTATUS_XU) 129 #define SDPCMD_INTSTATUS_DMA (SDPCMD_INTSTATUS_RI | \ 130 SDPCMD_INTSTATUS_XI | \ 131 SDPCMD_INTSTATUS_ERRORS) 132 #define SDPCMD_HOSTINTMASK 0x024 133 #define SDPCMD_INTMASK 0x028 134 #define SDPCMD_SBINTSTATUS 0x02c 135 #define SDPCMD_SBINTMASK 0x030 136 #define SDPCMD_FUNCTINTMASK 0x034 137 #define SDPCMD_TOSBMAILBOX 0x040 138 #define SDPCMD_TOSBMAILBOX_NAK (1 << 0) 139 #define SDPCMD_TOSBMAILBOX_INT_ACK (1 << 1) 140 #define SDPCMD_TOSBMAILBOX_USE_OOB (1 << 2) 141 #define SDPCMD_TOSBMAILBOX_DEV_INT (1 << 3) 142 #define SDPCMD_TOHOSTMAILBOX 0x044 143 #define SDPCMD_TOSBMAILBOXDATA 0x048 144 #define SDPCMD_TOHOSTMAILBOXDATA 0x04C 145 #define SDPCMD_TOHOSTMAILBOXDATA_NAKHANDLED (1 << 0) 146 #define SDPCMD_TOHOSTMAILBOXDATA_DEVREADY (1 << 1) 147 #define SDPCMD_TOHOSTMAILBOXDATA_FC (1 << 2) 148 #define SDPCMD_TOHOSTMAILBOXDATA_FWREADY (1 << 3) 149 #define SDPCMD_TOHOSTMAILBOXDATA_FWHALT (1 << 4) 150 151 struct bwfm_sdio_hwhdr { 152 uint16_t frmlen; 153 uint16_t cksum; 154 }; 155 156 struct bwfm_sdio_hwexthdr { 157 uint16_t pktlen; 158 uint8_t res0; 159 uint8_t flags; 160 uint16_t res1; 161 uint16_t padlen; 162 }; 163 164 struct bwfm_sdio_swhdr { 165 uint8_t seqnr; 166 uint8_t chanflag; /* channel + flag */ 167 #define BWFM_SDIO_SWHDR_CHANNEL_CONTROL 0x00 168 #define BWFM_SDIO_SWHDR_CHANNEL_EVENT 0x01 169 #define BWFM_SDIO_SWHDR_CHANNEL_DATA 0x02 170 #define BWFM_SDIO_SWHDR_CHANNEL_GLOM 0x03 171 #define BWFM_SDIO_SWHDR_CHANNEL_TEST 0x0F 172 #define BWFM_SDIO_SWHDR_CHANNEL_MASK 0x0F 173 uint8_t nextlen; 174 uint8_t dataoff; 175 uint8_t flowctl; 176 uint8_t maxseqnr; 177 uint16_t res0; 178 }; 179 180 struct bwfm_sdio_sdpcm { 181 uint32_t flags; 182 uint32_t trap_addr; 183 uint32_t assert_exp_addr; 184 uint32_t assert_file_addr; 185 uint32_t assert_line; 186 uint32_t console_addr; 187 uint32_t msgtrace_addr; 188 uint8_t tag[32]; 189 uint32_t brpt_addr; 190 }; 191 192 struct bwfm_sdio_console { 193 uint32_t vcons_in; 194 uint32_t vcons_out; 195 uint32_t log_buf; 196 uint32_t log_bufsz; 197 uint32_t log_idx; 198 }; 199