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Searched refs:SETEQ (Results 1 – 25 of 67) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td73 defm EQ : ComparisonInt<SETEQ, "eq ", 0x46, 0x51>;
90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1448 SETEQ, // 1 X 0 0 1 True if equal enumerator
1474 return Code == SETEQ || Code == SETNE; in isIntEqualitySetCC()
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp317 case ISD::SETEQ: in softenSetCCOperands()
3848 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
4286 Cond = ISD::SETEQ; in SimplifySetCC()
4349 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
4456 case ISD::SETEQ: in SimplifySetCC()
4477 case ISD::SETEQ: in SimplifySetCC()
4567 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
4586 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; in SimplifySetCC()
4603 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
4609 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); in SimplifySetCC()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVE.h212 case ISD::SETEQ: in intCondCode2Icc()
242 case ISD::SETEQ: in fpCondCode2Fcc()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DAnalysis.cpp211 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
223 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
240 case ISD::SETEQ: in getICmpCondCode()
H A DTargetLoweringBase.cpp670 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
671 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
672 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
673 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td310 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
314 def : PatSetCC<FPR64, any_fsetcc, SETEQ, FEQ_D>;
322 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ),
329 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ),
H A DRISCVInstrInfoZfh.td310 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
314 def : PatSetCC<FPR16, any_fsetcc, SETEQ, FEQ_H>;
322 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ),
329 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ),
H A DRISCVISelDAGToDAG.h118 case ISD::SETEQ: in getRISCVCCForIntCC()
H A DRISCVInstrInfoF.td559 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
563 def : PatSetCC<FPR32, any_fsetcc, SETEQ, FEQ_S>;
571 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ),
578 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ),
H A DRISCVInstrInfoVSDPatterns.td680 defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
688 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
698 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSEQ", SETEQ>;
953 defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
/openbsd/gnu/llvm/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td293 def BEQ : Branch_RR<0x01, "beq", SETEQ>;
300 def BEQI : Branch_RI<0x02, "beqi", SETEQ>;
307 def BEQZ : Branch_RZ<0x01, 0x00, "beqz", SETEQ>;
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3175 case ISD::SETEQ: { in get32BitZExtCompare()
3349 case ISD::SETEQ: { in get32BitSExtCompare()
3520 case ISD::SETEQ: { in get64BitZExtCompare()
3677 case ISD::SETEQ: { in get64BitSExtCompare()
4068 case ISD::SETEQ: in SelectCC()
4095 case ISD::SETEQ: in SelectCC()
4144 case ISD::SETEQ: in getPredicateForSetCC()
4231 case ISD::SETEQ: in getVCmpInst()
4275 case ISD::SETEQ: in getVCmpInst()
4376 case ISD::SETEQ: in trySETCC()
[all …]
H A DPPCInstrInfo.td3403 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3501 defm : ExtSetCCPat<SETEQ,
3611 defm : ExtSetCCShiftPat<SETEQ,
3632 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3646 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3658 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3672 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3698 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3787 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)),
3831 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)),
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td365 defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, MVCV32, 1>;
448 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
450 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)),
452 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td345 defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, MVCV32>;
406 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
408 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)),
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td171 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
173 def : PatFPSetcc<SETEQ, FCMP_CEQ_S, FPR32>;
H A DLoongArchFloat64InstrInfo.td172 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
174 def : PatFPSetcc<SETEQ, FCMP_CEQ_D, FPR64>;
/openbsd/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1467 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition()
1525 case ISD::SETEQ: in TranslateIntegerM68kCC()
1604 case ISD::SETEQ: in TranslateM68kCC()
1955 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1966 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1985 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2292 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && in LowerBRCOND()
/openbsd/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp811 case ISD::SETEQ: in IntCondCCodeToICC()
1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS()
1316 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSRL_PARTS()
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1412 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1418 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1425 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1431 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1248 X86_INTRINSIC_DATA(sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ),
1265 X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ),
1273 X86_INTRINSIC_DATA(sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ),
1320 X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ),
/openbsd/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp199 { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ }, in MSP430TargetLowering()
205 { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ }, in MSP430TargetLowering()
1050 case ISD::SETEQ: in EmitCMP()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td325 def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;
362 def COND_EQ : PatFrags<(ops), [(OtherVT SETEQ), (OtherVT SETUEQ)]>;
H A DAMDGPUISelLowering.cpp1426 case ISD::SETEQ: in combineFMinMaxLegacy()
1922 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ); in LowerUDIVREM64()
1944 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ); in LowerUDIVREM64()
1978 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ); in LowerUDIVREM64()
1982 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ); in LowerUDIVREM64()
2756 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ); in LowerFP_TO_FP16()
2790 One, Zero, ISD::SETEQ); in LowerFP_TO_FP16()
2799 I, V, ISD::SETEQ); in LowerFP_TO_FP16()
3632 if (CCOpcode == ISD::SETEQ && in performCtlz_CttzCombine()

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