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Searched refs:SIEncodingFamily (Results 1 – 17 of 17) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td30 : EXPCommon<row, done>, SIMCInstr<NAME, SIEncodingFamily.NONE> {
69 : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.SI>, EXPe_ComprVM {
83 : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
98 : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.GFX10>, EXPe_ComprVM {
112 : EXP_Real_Row<_row, _done, pseudo, SIEncodingFamily.GFX11>, EXPe_Row {
H A DVOP2Instructions.td1242 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX11>,
1286 VOP2_Real<ps, SIEncodingFamily.GFX11, asmName>,
1296 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1307 SIEncodingFamily.GFX11> {
1326 VOP2_Real<ps, SIEncodingFamily.GFX11>,
1513 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1848 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1853 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1992 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1998 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
[all …]
H A DVOP3Instructions.td938 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
943 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>,
958 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
963 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1071 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1076 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1099 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1104 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1184 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
1206 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
[all …]
H A DVOP1Instructions.td705 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX11>,
711 VOP1_Real<ps, SIEncodingFamily.GFX11>,
723 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX11>,
836 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX10>,
919 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
924 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
953 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
958 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1051 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
1059 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
[all …]
H A DLDSDIRInstructions.td65 SIMCInstr<opName, SIEncodingFamily.NONE> {
109 def _gfx11 : LDSDIR_Real<op, lds, SIEncodingFamily.GFX11> {
H A DVOPInstructions.td61 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {
554 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> {
588 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
653 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
770 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> {
1334 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1338 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1347 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1358 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1362 VOP3_Real<ps, SIEncodingFamily.GFX11>,
[all …]
H A DVOPCInstructions.td135 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
1310 def _e32_gfx11 : VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1312 def _e64_gfx11 : VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1400 VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name#"_e32">,
1407 VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
1505 VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1511 VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1544 SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
1565 : VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>,
1574 : VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
[all …]
H A DVOP3PInstructions.td898 SIEncodingFamily.GFX11, asmName>,
907 SIEncodingFamily.GFX11> {
954 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
963 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
977 def _gfx90a_acd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
980 …def _gfx90a_vcd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64"), SIEncodingFamily.GFX90…
1011 def _gfx940_acd : VOP3P_Real<PS_ACD, SIEncodingFamily.GFX940>,
1014 def _gfx940_vcd : VOP3P_Real<PS_VCD, SIEncodingFamily.GFX940>,
1027 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1036 def _gfx940 : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
[all …]
H A DSIInstrInfo.td20 // SIEncodingFamily enum in SIInstrInfo.cpp and the columns of the
22 def SIEncodingFamily {
2768 SIMCInstr<opName, SIEncodingFamily.NONE> {
2785 SIMCInstr<opName, SIEncodingFamily.VI> {
2885 let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
2887 let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
2888 [!cast<string>(SIEncodingFamily.VI)],
2889 [!cast<string>(SIEncodingFamily.SDWA)],
2890 [!cast<string>(SIEncodingFamily.SDWA9)],
2895 [!cast<string>(SIEncodingFamily.GFX80)],
[all …]
H A DSMInstructions.td33 SIMCInstr<opName, SIEncodingFamily.NONE> {
460 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
509 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
564 int Subtarget = SIEncodingFamily.GFX9;
794 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
982 : SMEM_Real_10Plus_common<op, ps, ps.Mnemonic, SIEncodingFamily.GFX10,
1185 SMEM_Real_10Plus_common<op, ps, opName, SIEncodingFamily.GFX11,
H A DBUFInstructions.td51 SIMCInstr<opName, SIEncodingFamily.NONE> {
2081 Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10> {
2087 Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
2621 Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.SI> {
2682 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.VI, has_sccb> {
2691 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.GFX90A, has_sccb> {
2701 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.GFX940> {
2771 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> {
2948 MTBUF_Real_Base_vi <op, ps, SIEncodingFamily.VI> {
2956 MTBUF_Real_Base_vi <op, ps, SIEncodingFamily.GFX90A> {
[all …]
H A DVINTERPInstructions.td178 VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX11>,
H A DDSInstructions.td11 SIMCInstr <opName, SIEncodingFamily.NONE> {
1213 SIEncodingFamily.GFX11>;
1217 …def _gfx11 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11<op, backing_pseudo, SIEncodingFamily.GFX11, real_n…
1286 SIEncodingFamily.GFX10>;
1321 SIEncodingFamily.SI>;
1347 SIEncodingFamily.SI>;
1509 SIMCInstr <ps.Mnemonic, SIEncodingFamily.VI> {
H A DVOPDInstructions.td61 SIMCInstr<NAME, SIEncodingFamily.GFX11> {
H A DSIInstrInfo.cpp7992 enum SIEncodingFamily { enum
8012 return SIEncodingFamily::SI; in subtargetEncodingFamily()
8015 return SIEncodingFamily::VI; in subtargetEncodingFamily()
8017 return SIEncodingFamily::GFX10; in subtargetEncodingFamily()
8019 return SIEncodingFamily::GFX11; in subtargetEncodingFamily()
8045 SIEncodingFamily Gen = subtargetEncodingFamily(ST); in pseudoToMCOpcode()
8049 Gen = SIEncodingFamily::GFX9; in pseudoToMCOpcode()
8055 Gen = SIEncodingFamily::GFX80; in pseudoToMCOpcode()
8060 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
8063 Gen = SIEncodingFamily::SDWA9; in pseudoToMCOpcode()
[all …]
H A DFLATInstructions.td24 SIMCInstr<opName, SIEncodingFamily.NONE> {
1587 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
1655 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
1672 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX940> {
1927 FLAT_Real<op, ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {
2163 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX11> {
H A DSOPInstructions.td25 SIMCInstr<opName, SIEncodingFamily.NONE> {
1490 class Select_gfx11<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX11> {
1495 class Select_gfx10<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX10> {
1500 class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> {
1505 class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {