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Searched refs:SINT_TO_FP (Results 1 – 25 of 39) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp682 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
768 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
770 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
772 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
774 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
776 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
778 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
780 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
782 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
784 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp174 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
179 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
305 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
457 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
468 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
5973 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
5975 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
5993 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
9625 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
10428 case ISD::SINT_TO_FP: in LowerOperation()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2175 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
2176 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
2287 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
2288 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
2289 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
2290 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
2291 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
2292 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
2293 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
2294 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
H A DREADME-FPStack.txt49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
H A DX86ISelLowering.cpp945 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
2395 ISD::SINT_TO_FP, in X86TargetLowering()
21042 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP_AVX512DQ()
21084 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP16()
21121 case ISD::SINT_TO_FP: in useVectorCast()
30156 if (Op->getOpcode() == ISD::SINT_TO_FP || in LowerWin64_INT128_TO_FP()
33904 case ISD::SINT_TO_FP: in ReplaceNodeResults()
53989 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineUIntToFP()
54036 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineSIntToFP()
55859 if (InOpcode == ISD::SINT_TO_FP && in combineEXTRACT_SUBVECTOR()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1883 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
1884 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
1885 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
1891 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1892 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1893 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1899 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
1900 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
1906 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
1915 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp504 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
505 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
506 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
1223 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1312 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1779 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForStreamingSVE()
1903 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
5946 case ISD::SINT_TO_FP: in LowerOperation()
15940 bool IsSigned = Opc == ISD::SINT_TO_FP; in performFDivCombine()
21425 case ISD::SINT_TO_FP: in PerformDAGCombine()
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DConstrainedOps.def58 DAG_INSTRUCTION(SIToFP, 1, 1, experimental_constrained_sitofp, SINT_TO_FP)
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h773 SINT_TO_FP, enumerator
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp429 case ISD::SINT_TO_FP: in LegalizeOp()
545 case ISD::SINT_TO_FP: in Promote()
1418 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) == in ExpandUINT_TO_FLOAT()
1481 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI); in ExpandUINT_TO_FLOAT()
1483 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO); in ExpandUINT_TO_FLOAT()
H A DLegalizeDAG.cpp1004 case ISD::SINT_TO_FP: in LegalizeOp()
2319 Node->getOpcode() == ISD::SINT_TO_FP); in ExpandLegalINT_TO_FP()
2447 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or); in ExpandLegalINT_TO_FP()
2449 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2472 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2537 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP || in PromoteLegalINT_TO_FP()
2993 case ISD::SINT_TO_FP: in ExpandNode()
4274 case ISD::SINT_TO_FP: in ConvertNodeToLibcall()
4278 bool Signed = Node->getOpcode() == ISD::SINT_TO_FP || in ConvertNodeToLibcall()
4485 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
[all …]
H A DLegalizeFloatTypes.cpp137 case ISD::SINT_TO_FP: in SoftenFloatResult()
769 bool Signed = N->getOpcode() == ISD::SINT_TO_FP || in SoftenFloatRes_XINT_TO_FP()
1274 case ISD::SINT_TO_FP: in ExpandFloatResult()
1672 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP || in ExpandFloatRes_XINT_TO_FP()
2299 case ISD::SINT_TO_FP: in PromoteFloatResult()
2663 case ISD::SINT_TO_FP: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp357 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
H A DFastISel.cpp310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1780 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
H A DLegalizeVectorTypes.cpp109 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
648 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
1063 case ISD::SINT_TO_FP: in SplitVectorResult()
2837 case ISD::SINT_TO_FP: in SplitVectorOperand()
4060 case ISD::SINT_TO_FP: in WidenVectorResult()
5820 case ISD::SINT_TO_FP: in WidenVectorOperand()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp253 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
326 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
427 setOperationAction(ISD::SINT_TO_FP, VecTy, Custom); in initializeHVXLowering()
2302 assert(Op.getOpcode() == ISD::SINT_TO_FP || in LowerHvxIntToFp()
2677 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in EqualizeFpIntConversion()
2687 bool Signed = Opc == ISD::FP_TO_SINT || Opc == ISD::SINT_TO_FP; in EqualizeFpIntConversion()
2828 assert(Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in ExpandHvxIntToFp()
2862 bool Signed = Opc == ISD::SINT_TO_FP; in ExpandHvxIntToFp()
3153 case ISD::SINT_TO_FP: in LowerHvxOperation()
3235 case ISD::SINT_TO_FP: in LowerHvxOperation()
[all …]
H A DHexagonISelLowering.cpp1772 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1773 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1774 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp168 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
254 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
1886 case ISD::SINT_TO_FP: in LowerConvertLow()
2367 N->getOpcode() == ISD::SINT_TO_FP); in performVectorExtendToFPCombine()
2671 case ISD::SINT_TO_FP: in PerformDAGCombine()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp255 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
277 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
526 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
8366 if (UI->getOpcode() != ISD::SINT_TO_FP && in directMoveIsProfitable()
8379 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in convertIntToFP()
8415 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FPDirectMove()
8505 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FP()
14559 if (FirstInput.getOpcode() != ISD::SINT_TO_FP && in DAGCombineBuildVector()
14601 assert((N->getOpcode() == ISD::SINT_TO_FP || in combineFPToIntToFP()
14627 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in combineFPToIntToFP()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1647 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1649 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3211 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3587 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3594 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp409 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
430 ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP, in AMDGPUTargetLowering()
1267 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1709 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2512 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
2549 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2612 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp961 case ISD::SINT_TO_FP: in getCastInstrCost()
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp182 setOperationAction(ISD::SINT_TO_FP, GRLenVT, Custom); in LoongArchTargetLowering()
248 case ISD::SINT_TO_FP: in LowerOperation()
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp415 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
416 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
435 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
436 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
659 ISD::SINT_TO_FP, in SystemZTargetLowering()
7145 case ISD::SINT_TO_FP: in PerformDAGCombine()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1839 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()

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