| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 331 SMULO, enumerator
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| H A D | SelectionDAGNodes.h | 3121 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
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| /openbsd/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 98 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
1358 case ISD::SMULO: in LowerOperation()
2145 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
2172 case ISD::SMULO: in LowerSELECT()
2371 case ISD::SMULO: in LowerBRCOND()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 402 case ISD::SMULO: in LegalizeOp()
878 case ISD::SMULO: in Expand()
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| H A D | SelectionDAGDumper.cpp | 316 case ISD::SMULO: return "smulo"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 189 case ISD::SMULO: in PromoteIntegerResult()
1517 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO()
2530 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()
3832 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
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| H A D | LegalizeVectorTypes.cpp | 181 case ISD::SMULO: in ScalarizeVectorResult()
1145 case ISD::SMULO: in SplitVectorResult()
4027 case ISD::SMULO: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 3288 case ISD::SMULO: in computeKnownBits()
4233 case ISD::SMULO: in ComputeNumSignBits()
11469 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
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| H A D | TargetLowering.cpp | 9680 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) { in expandFixedPointMul()
9682 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul()
9973 bool isSigned = Node->getOpcode() == ISD::SMULO; in expandMULO()
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| H A D | LegalizeDAG.cpp | 3540 case ISD::SMULO: { in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 6902 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; in visitIntrinsicCall()
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| H A D | DAGCombiner.cpp | 1725 case ISD::SMULO: in visit()
5035 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
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| /openbsd/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1823 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
3117 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3119 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
3247 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 821 ISD::SMULO, ISD::UMULO}, in initActions()
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 724 setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom); in SITargetLowering()
4784 case ISD::SMULO: in LowerOperation()
5383 bool isSigned = Op.getOpcode() == ISD::SMULO; in lowerXMULO()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 622 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering()
623 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering()
3580 case ISD::SMULO: in getAArch64XALUOOp()
3583 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp()
5855 case ISD::SMULO: in LowerOperation()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1045 setOperationAction(ISD::SMULO, MVT::v16i8, Custom); in X86TargetLowering()
1262 setOperationAction(ISD::SMULO, MVT::v2i32, Custom); in X86TargetLowering()
1466 setOperationAction(ISD::SMULO, MVT::v32i8, Custom); in X86TargetLowering()
1793 setOperationAction(ISD::SMULO, MVT::v64i8, Custom); in X86TargetLowering()
2294 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering()
25426 case ISD::SMULO: in getX86XALUOOp()
25711 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
29924 bool IsSigned = Op->getOpcode() == ISD::SMULO; in LowerMULO()
33282 case ISD::SMULO: in LowerOperation()
33398 case ISD::SMULO: in ReplaceNodeResults()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4947 case ISD::SMULO: in getARMXALUOOp()
5690 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND()
5741 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()
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