Searched refs:SPE_VECTOR_MODE (Results 1 – 6 of 6) sorted by relevance
510 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) ? 64 : ALIGN)820 #define SPE_VECTOR_MODE(MODE) \ macro848 : SPE_VECTOR_MODE (MODE1) \849 ? SPE_VECTOR_MODE (MODE2) \850 : SPE_VECTOR_MODE (MODE2) \851 ? SPE_VECTOR_MODE (MODE1) \1146 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
2994 else if (SPE_VECTOR_MODE (mode) in rs6000_legitimize_address()3400 && !SPE_VECTOR_MODE (mode) in rs6000_legitimize_reload_address()3434 && !SPE_VECTOR_MODE (mode) in rs6000_legitimize_reload_address()3535 && !SPE_VECTOR_MODE (mode) in rs6000_legitimate_address()4523 else if (SPE_VECTOR_MODE (mode) in function_arg_boundary()5283 && (SPE_VECTOR_MODE (mode) in function_arg()13328 if (SPE_VECTOR_MODE (mode)) in spe_func_has_64bit_regs_p()14192 && SPE_VECTOR_MODE (mode) in emit_frame_save()14229 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) in gen_frame_mem_offset()19431 && (SPE_VECTOR_MODE (GET_MODE (reg)) in rs6000_dwarf_register_span()[all …]
286 if (SPE_VECTOR_MODE (mode))
888 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \900 #define SPE_VECTOR_MODE(MODE) \ macro911 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \926 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \1350 : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 \2087 && (! SPE_VECTOR_MODE (MODE) \
2152 else if (SPE_VECTOR_MODE (mode))2277 && !SPE_VECTOR_MODE (mode)2366 && !SPE_VECTOR_MODE (mode)2978 else if (SPE_VECTOR_MODE (mode))3006 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)3150 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) && named)3189 && SPE_VECTOR_MODE (mode) && !named)10216 && SPE_VECTOR_MODE (mode)10257 if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13208 * config/rs60000/rs6000.c (SPE_VECTOR_MODE): Include V1DImode.18002 Add case for SPE_VECTOR_MODE.18089 (SPE_VECTOR_MODE): New.