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Searched refs:SR_INT_ENAB (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/arch/mips64/mips64/
H A Dexception.S183 and t0, a1, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
212 and t0, a1, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
222 LI v0, ~SR_INT_ENAB
232 ori t0, SR_INT_ENAB # enable interrupts for handling AST
288 and t0, a1, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
296 LI t1, ~SR_INT_ENAB
322 and t0, a1, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
331 LI t1, ~SR_INT_ENAB
342 ori t0, SR_INT_ENAB # enable interrupts for handling AST
H A Dcp0access.S104 or v1, v0, SR_INT_ENAB
115 and v1, v0, ~SR_INT_ENAB
134 ori v1, SR_INT_ENAB # enable interrupts
H A Dtlbhandler.S318 ori v0, v1, SR_INT_ENAB
319 xori v0, v0, SR_INT_ENAB
371 ori v0, v1, SR_INT_ENAB
372 xori v0, v0, SR_INT_ENAB
416 ori v0, v1, SR_INT_ENAB
417 xori v0, v0, SR_INT_ENAB
498 ori v0, v1, SR_INT_ENAB
499 xori v0, v0, SR_INT_ENAB
H A Dcontext.S119 ori s1, SR_INT_ENAB
120 xori s1, SR_INT_ENAB
271 ori v0, v0, SR_INT_ENAB
295 LI t1, ~SR_INT_ENAB
H A Dinterrupt.c113 if (!(trapframe->sr & SR_INT_ENAB)) in interrupt()
H A Dmips64_machdep.c134 SR_KX | SR_INT_ENAB;
H A Dtrap.c196 if (ISSET(trapframe->sr, SR_INT_ENAB)) in trap()
467 if (trapframe->sr & SR_INT_ENAB) { in itsa()
/openbsd/sys/arch/loongson/loongson/
H A Dlocore.S46 li v1, ~SR_INT_ENAB
101 li v1, ~SR_INT_ENAB
/openbsd/sys/arch/mips64/include/
H A Dmips_cpu.h73 #define SR_INT_ENAB 0x00000001 macro
/openbsd/sys/arch/octeon/octeon/
H A Dlocore.S69 li v1, ~(SR_INT_ENAB | SR_ERL | SR_EXL)