| /openbsd/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 773 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
774 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
775 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 902 unsigned ShiftOp; in PromoteIntRes_ADDSUBSHLSAT() local
907 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
910 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
928 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
973 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX() local
974 return DAG.getNode(ShiftOp, dl, PromotedType, Result, in PromoteIntRes_MULFIX()
4309 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
4311 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4312 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
4314 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| H A D | DAGCombiner.cpp | 2384 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2388 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2393 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2394 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
6188 if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse()) in foldLogicOfShifts()
6192 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6202 SDValue X1 = ShiftOp.getOperand(0); in foldLogicOfShifts()
6203 SDValue Y = ShiftOp.getOperand(1); in foldLogicOfShifts()
8024 if (!ShiftOp) in calculateByteProvider()
8027 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
[all …]
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| H A D | SelectionDAGBuilder.cpp | 2895 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2904 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2910 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2915 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
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| /openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1915 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1916 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
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| /openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3332 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3377 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7303 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; in lowerSMULH_UMULH() local
7306 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 219 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
223 setOperationAction(ShiftOp , MVT::i8 , Custom); in X86TargetLowering()
224 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
225 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction); in X86TargetLowering()
227 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction); in X86TargetLowering()
49876 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
49877 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
49881 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19436 SDValue ShiftOp = Index.getOperand(1); in foldIndexIntoBase() local
19438 if (auto Shift = DAG.getSplatValue(ShiftOp)) in foldIndexIntoBase()
19444 Add.getOperand(0), ShiftOp); in foldIndexIntoBase()
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