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Searched refs:ShiftVal (Results 1 – 25 of 25) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp283 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
284 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
287 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
304 ShiftVal = 12; in getAddSubImmOpValue()
306 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
600 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
601 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
606 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
627 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
628 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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H A DAArch64InstPrinter.cpp1257 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1269 if (ShiftVal != 0) in printArithExtend()
1270 O << ", lsl " << markup("<imm:") << "#" << ShiftVal << markup(">"); in printArithExtend()
1275 if (ShiftVal != 0) in printArithExtend()
1276 O << " " << markup("<imm:") << "#" << ShiftVal << markup(">"); in printArithExtend()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp380 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
381 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); in getIntMatCost()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h314 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
315 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
329 unsigned &ShiftVal);
330 void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1554 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchShiftOfShiftedLogic()
1632 ShiftVal = MaybeImmVal->Value.exactLogBase2(); in matchCombineMulToShl()
1633 return (static_cast<int32_t>(ShiftVal) != -1); in matchCombineMulToShl()
1641 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
1942 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchCombineShiftToUnmerge()
1943 return ShiftVal >= Size / 2 && ShiftVal < Size; in matchCombineShiftToUnmerge()
1953 assert(ShiftVal >= HalfSize); in applyCombineShiftToUnmerge()
1959 unsigned NarrowShiftAmt = ShiftVal - HalfSize; in applyCombineShiftToUnmerge()
1995 if (ShiftVal == HalfSize) { in applyCombineShiftToUnmerge()
1999 } else if (ShiftVal == Size - 1) { in applyCombineShiftToUnmerge()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1258 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1263 ShiftVal, SetFlags, WantResult); in emitAddSub()
1280 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1286 ShiftVal, SetFlags, WantResult); in emitAddSub()
1642 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
4621 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4649 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4684 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
4715 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4718 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
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H A DAArch64ISelDAGToDAG.cpp607 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
608 if (ShiftVal > 3) in isWorthFoldingSHL()
974 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
981 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
982 if (ShiftVal > 4) in SelectArithExtendedRegister()
1018 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
1027 unsigned ShiftVal = 0; in SelectArithUXTXRegister() local
1036 ShiftVal = CSD->getZExtValue(); in SelectArithUXTXRegister()
1037 if (ShiftVal > 4) in SelectArithUXTXRegister()
1256 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
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H A DAArch64InstrInfo.cpp889 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
890 if (ShiftVal == 0) in isFalkorShiftExtFast()
892 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
916 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
917 return ShiftVal == 0 || in isFalkorShiftExtFast()
918 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
924 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
925 return ShiftVal == 0 || in isFalkorShiftExtFast()
926 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
H A DAArch64TargetTransformInfo.cpp186 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
187 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp788 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
789 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal); in CreateWideLoad()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2150 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2155 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
2171 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2172 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
2176 ReplaceNode(N, getBFE32(false, SDLoc(N), And.getOperand(0), ShiftVal, in SelectS_BFE()
H A DAMDGPUISelLowering.cpp4241 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
4243 BitsFrom, ShiftVal); in PerformDAGCombine()
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2290 auto ShiftVal = DAG.getSplatValue(Op.getOperand(1)); in LowerShift() local
2291 if (!ShiftVal) in LowerShift()
2295 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32); in LowerShift()
2312 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal); in LowerShift()
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2508 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2517 ShiftVal = Amount; in isSimpleShift()
2666 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2669 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2670 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2671 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2677 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2680 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2681 (MaskVal << ShiftVal != 0) && in adjustForTestUnderMask()
2682 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal && in adjustForTestUnderMask()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp389 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
390 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
396 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
H A DX86ISelLowering.cpp8629 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
20190 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
20201 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
31539 if (!ShiftVal) in FindSingleBitChange()
31541 if (ShiftVal->equalsInt(1)) in FindSingleBitChange()
38186 if (ShiftVal.uge(VTBits)) in ComputeNumSignBitsForTargetNode()
38189 if (ShiftVal.uge(Tmp)) in ComputeNumSignBitsForTargetNode()
38200 ShiftVal += Tmp; in ComputeNumSignBitsForTargetNode()
38201 return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); in ComputeNumSignBitsForTargetNode()
48319 if (!ShiftVal) in combineVectorShiftImm()
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H A DX86TargetTransformInfo.cpp5521 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
5522 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/openbsd/gnu/llvm/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp537 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
540 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
547 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
H A DInstCombineCompares.cpp2069 const APInt *ShiftVal; in foldICmpShlConstant() local
2070 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
2071 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
/openbsd/gnu/llvm/llvm/lib/IR/
H A DAutoUpgrade.cpp1371 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86ALIGNIntrinsics() local
1380 ShiftVal &= (NumElts - 1); in UpgradeX86ALIGNIntrinsics()
1384 if (ShiftVal >= 32) in UpgradeX86ALIGNIntrinsics()
1389 if (ShiftVal > 16) { in UpgradeX86ALIGNIntrinsics()
1390 ShiftVal -= 16; in UpgradeX86ALIGNIntrinsics()
1399 unsigned Idx = ShiftVal + i; in UpgradeX86ALIGNIntrinsics()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5167 unsigned ShiftVal = 0; in Select() local
5172 ShiftVal = 1; in Select()
5176 ShiftVal = 1; in Select()
5181 ShiftVal = 3; in Select()
5185 ShiftVal = 3; in Select()
5190 ShiftVal = 2; in Select()
5194 ShiftVal = 2; in Select()
5226 SDValue Ops[] = {Move, getI32Imm((32 - (4 + ShiftVal)) & 31, dl), in Select()
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1984 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2000 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp6613 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local
6616 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
6704 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
6721 ShiftVal = *MaybeShiftVal; in selectArithExtendedRegister()
6722 if (ShiftVal > 4) in selectArithExtendedRegister()
6758 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()
/openbsd/gnu/llvm/clang/lib/CodeGen/
H A DCGBuiltin.cpp14081 if (ShiftVal >= 32) in EmitX86BuiltinExpr()
14086 if (ShiftVal > 16) { in EmitX86BuiltinExpr()
14087 ShiftVal -= 16; in EmitX86BuiltinExpr()
14096 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
14117 ShiftVal &= NumElts - 1; in EmitX86BuiltinExpr()
14121 Indices[i] = i + ShiftVal; in EmitX86BuiltinExpr()
14203 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
14232 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
14259 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
14280 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
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/openbsd/gnu/llvm/llvm/lib/Analysis/
H A DValueTracking.cpp2623 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1); in isKnownNonZero() local
2625 if (Known.countMaxLeadingZeros() < BitWidth - ShiftVal) in isKnownNonZero()
2628 if (Known.countMinTrailingZeros() >= ShiftVal) in isKnownNonZero()