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Searched refs:SrcR (Results 1 – 7 of 7) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp468 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} in IFRecord()
470 unsigned SrcR, InsR; member
486 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
864 for (unsigned SrcR : AVs) { in findRecordInsertForms() local
866 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR); in findRecordInsertForms()
899 if (!isValidInsertForm(VR, SrcR, InsR, L, S)) in findRecordInsertForms()
992 if (R == IF.SrcR || R == IF.InsR) in findRemovableRegisters()
1237 unsigned OSA = BaseOrd[A.first.SrcR], OSB = BaseOrd[B.first.SrcR]; in operator ()()
1370 unsigned SR = LL[0].first.SrcR, IR = LL[0].first.InsR; in selectCandidates()
1417 .addReg(IF.SrcR) in generateInserts()
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H A DRDFCopy.cpp47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
49 assert(Register::isPhysicalRegister(SrcR.Reg)); in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
H A DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY() argument
114 EM.insert(std::make_pair(DstR, SrcR)); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonFrameLowering.cpp1722 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1724 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1746 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1756 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1809 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1825 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1896 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1897 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2()
1898 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2()
1985 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
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H A DHexagonBitSimplify.cpp2245 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
2254 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) in genBitSplit()
2273 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) in genBitSplit()
2290 if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I) in genBitSplit()
2305 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) in genBitSplit()
2307 if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1)) in genBitSplit()
2317 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR) in genBitSplit()
2336 .addReg(SrcR, 0, SrcSR) in genBitSplit()
H A DHexagonConstPropagation.cpp1943 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
1944 bool Eval = evaluateCOPY(SrcR, Inputs, RC); in evaluate()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp733 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA() local
735 .add(SrcR) in processInstructionForSlowLEA()