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Searched refs:SubRegIdx (Results 1 – 25 of 30) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
349 if (SubRegIdx == 0) in computeMainRangesFixFlags()
H A DRegisterPressure.cpp534 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
537 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
542 SubRegIdx = 0; in collectOperandLanes()
546 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
548 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
552 void pushRegLanes(Register Reg, unsigned SubRegIdx, in pushRegLanes() argument
555 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
556 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1234 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1235 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DVirtRegMap.cpp396 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
397 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
398 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
H A DStackMaps.cpp268 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
269 if (SubRegIdx) in parseOperand()
270 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
H A DRegAllocFast.cpp867 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
868 if (SubRegIdx != 0) { in allocVirtRegUndef()
869 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
H A DMachineVerifier.cpp2396 const unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
2402 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() && in checkLiveness()
2444 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2445 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
2536 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2537 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
H A DRegisterCoalescer.cpp324 MachineOperand &MO, unsigned SubRegIdx);
1725 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1726 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
1879 unsigned SubRegIdx = MO.getSubReg(); in setUndefOnPrunedSubRegUses() local
1880 if (SubRegIdx == 0 || MO.isUndef()) in setUndefOnPrunedSubRegUses()
1883 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in setUndefOnPrunedSubRegUses()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp264 unsigned Opcode, SubRegIdx; in lowerVSPILL() local
270 SubRegIdx = RISCV::sub_vrm1_0; in lowerVSPILL()
274 SubRegIdx = RISCV::sub_vrm2_0; in lowerVSPILL()
278 SubRegIdx = RISCV::sub_vrm4_0; in lowerVSPILL()
306 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I)) in lowerVSPILL()
333 unsigned Opcode, SubRegIdx; in lowerVRELOAD() local
339 SubRegIdx = RISCV::sub_vrm1_0; in lowerVRELOAD()
343 SubRegIdx = RISCV::sub_vrm2_0; in lowerVRELOAD()
347 SubRegIdx = RISCV::sub_vrm4_0; in lowerVRELOAD()
371 TRI->getSubReg(DestReg, SubRegIdx + I)) in lowerVRELOAD()
H A DRISCVInstrInfo.cpp317 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
322 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
327 SubRegIdx = RISCV::sub_vrm4_0; in copyPhysReg()
332 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
337 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
342 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
347 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
352 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
357 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
362 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
[all …]
H A DRISCVISelDAGToDAG.cpp347 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG() local
349 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
391 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEGFF() local
393 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
446 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLXSEG() local
1708 unsigned SubRegIdx; in Select() local
1709 std::tie(SubRegIdx, Idx) = in Select()
1730 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
1761 unsigned SubRegIdx; in Select() local
1762 std::tie(SubRegIdx, Idx) = in Select()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1393 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeSMemLoadImmPair()
1394 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeSMemLoadImmPair()
1448 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeBufferLoadPair()
1449 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeBufferLoadPair()
1507 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferLoadPair()
1508 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferLoadPair()
1536 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferStorePair()
1537 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferStorePair()
1605 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeFlatLoadPair()
1606 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeFlatLoadPair()
[all …]
H A DAMDGPUInstructionSelector.cpp2241 int SubRegIdx = sizeToSubRegIndex(DstSize); in selectG_TRUNC() local
2242 if (SubRegIdx == -1) in selectG_TRUNC()
2248 = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx); in selectG_TRUNC()
2257 I.getOperand(1).setSubReg(SubRegIdx); in selectG_TRUNC()
H A DAMDGPUISelDAGToDAG.cpp383 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); in getOperandRegClass() local
385 SubRegIdx); in getOperandRegClass()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp197 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
203 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
211 if (SubRegIdx != X86::sub_8bit) in getSuperRegDestIfDead()
H A DX86ISelDAGToDAG.cpp1578 unsigned SubRegIdx = N->getConstantOperandVal(2); in PostprocessISelDAG() local
1579 if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) in PostprocessISelDAG()
5653 unsigned SubRegIdx; in Select() local
5669 SubRegIdx = 0; in Select()
5677 SubRegIdx = 0; in Select()
5686 SubRegIdx = X86::sub_8bit; in Select()
5692 SubRegIdx = X86::sub_16bit; in Select()
5698 SubRegIdx = X86::sub_32bit; in Select()
5709 if (SubRegIdx != 0) { in Select()
5711 CurDAG->getTargetExtractSubreg(SubRegIdx, dl, SubRegVT, Shift); in Select()
H A DX86InstrAVX512.td95 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
3205 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3206 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
3229 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3739 Narrow.SubRegIdx)>;
3748 Narrow.SubRegIdx)>;
10648 _.RC:$src, _.SubRegIdx)),
11481 _.info256.SubRegIdx)),
11482 _.info256.SubRegIdx)>;
11489 _.info128.SubRegIdx)),
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp330 const unsigned *SubRegIdx, in copyPhysSubRegs() argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); in copyPhysSubRegs()
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg() local
396 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local
402 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp475 CodeGenSubRegIndex *SubRegIdx; in computeSecondarySubRegs() local
477 std::tie(SubRegIdx, SubReg) = SubRegQueue.front(); in computeSecondarySubRegs()
495 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
497 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
498 if (SubRegIdx->ConcatenationOf.empty()) in computeSecondarySubRegs()
499 Parts.push_back(SubRegIdx); in computeSecondarySubRegs()
501 append_range(Parts, SubRegIdx->ConcatenationOf); in computeSecondarySubRegs()
H A DGlobalISelEmitter.cpp2857 const CodeGenSubRegIndex *SubRegIdx; member in __anon64c0a0e00111::TempRegRenderer
2866 SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {} in TempRegRenderer()
2873 if (SubRegIdx) { in emitRenderOpcodes()
2892 if (SubRegIdx) in emitRenderOpcodes()
2893 Table << MatchTable::NamedValue(SubRegIdx->getQualifiedName()); in emitRenderOpcodes()
2923 const CodeGenSubRegIndex *SubRegIdx; member in __anon64c0a0e00111::SubRegIndexRenderer
2927 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
2936 << MatchTable::IntValue(SubRegIdx->EnumValue) in emitRenderOpcodes()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h910 int64_t SubRegIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
913 0, SubRegIdx); in executeMatchTable()
917 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h645 unsigned SubRegIdx) const { in getSubRegisterClass() argument
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp1983 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local
1988 SubRegIdx), 0); in ExtendToInt64()
1997 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local
3071 SDValue SubRegIdx = in addExtOrTrunc() local
3074 ImDef, NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
3081 SDValue SubRegIdx = in addExtOrTrunc() local
3084 NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
5214 SDValue SubRegIdx = CurDAG->getTargetConstant(SubReg, dl, MVT::i32); in Select() local
5217 CR6Reg, SubRegIdx, BCDOp.getValue(1)), in Select()
5267 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_eq, dl, MVT::i32); in Select() local
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1177 unsigned SubRegIdx = in loadVectorConstant() local
1180 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp351 unsigned SubRegIdx);
353 unsigned SubRegIdx);
1609 unsigned SubRegIdx) { in SelectLoad() argument
1623 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1638 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad() argument
1662 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3331 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; in emitINSERT_DF_VIDX() local
3388 .addReg(LaneReg, 0, SubRegIdx); in emitINSERT_DF_VIDX()
3417 .addReg(LaneTmp2, 0, SubRegIdx); in emitINSERT_DF_VIDX()

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