| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1183 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair() local
1184 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1322 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1324 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1373 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSMemLoadImmPair()
1424 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
1479 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair()
1541 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferStorePair()
1591 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeFlatLoadPair()
1639 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeFlatStorePair()
[all …]
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| H A D | SIRegisterInfo.h | 254 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
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| H A D | SIInstrInfo.h | 71 const TargetRegisterClass *SuperRC,
77 const TargetRegisterClass *SuperRC,
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| H A D | SIRegisterInfo.cpp | 2816 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, in getCompatibleSubRegClass() argument
2821 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
2822 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr; in getCompatibleSubRegClass()
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| H A D | SIInstrInfo.cpp | 4997 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
5015 Register NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
5030 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
5042 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
5071 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
5072 if (!SuperRC) in isLegalRegOperand()
5075 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
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| H A D | AMDGPUISelDAGToDAG.cpp | 379 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
384 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 2898 const TargetRegisterClass *SuperRC, Register IdxReg, in computeIndirectRegIndex() argument
2912 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex()
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| H A D | SIISelLowering.cpp | 3761 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset() argument
3764 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 615 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
618 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
626 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
628 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
721 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
722 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| H A D | RegAllocGreedy.cpp | 1247 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1250 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1253 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1341 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1344 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1354 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
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| H A D | TargetLoweringBase.cpp | 1275 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1277 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1279 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1281 BestRC = SuperRC; in findRepresentativeClass()
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| H A D | MachineVerifier.cpp | 2229 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
2231 if (!SuperRC) { in visitMachineOperand()
2235 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 583 const TargetRegisterClass *SuperRC = nullptr; in combine() local
585 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
589 SuperRC = &Hexagon::HvxWRRegClass; in combine()
595 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
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| H A D | HexagonRegisterInfo.cpp | 439 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
440 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
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| /openbsd/gnu/llvm/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 411 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
412 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 644 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass() argument
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