1 /* $OpenBSD: uperf_sbusreg.h,v 1.4 2024/09/04 07:54:52 mglocker Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Effort sponsored in part by the Defense Advanced Research Projects 29 * Agency (DARPA) and Air Force Research Laboratory, Air Force 30 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 31 * 32 */ 33 34 /* 35 * System Controller registers (for both uni- and dual- processor versions) 36 */ 37 38 /* 39 * Ebus interface registers 40 */ 41 #define USC_ADDR 0x0000 42 #define USC_DATA 0x0004 43 44 /* Indirect registers */ 45 #define USC_CTRL 0x00 /* overall: control */ 46 #define USC_ID 0x04 /* overall: identity */ 47 #define USC_PERF0 0x08 /* overall: perf counter 0 */ 48 #define USC_PERF1 0x0c /* overall: perf connter 1 */ 49 #define USC_PERFSHAD 0x10 /* overall: perf shadow */ 50 #define USC_PERFCTRL 0x20 /* overall: perf control */ 51 #define USC_DBGPIN 0x30 /* overall: debug pin control */ 52 #define USC_P0CFG 0x40 /* port/processor 1 config */ 53 #define USC_P0STS 0x44 /* port/processor 0 status */ 54 #define USC_P1CFG 0x48 /* port/processor 1 config */ 55 #define USC_P1STS 0x4c /* port/processor 1 status */ 56 #define USC_SYSIOCFG 0x50 /* sysio/u2s port config */ 57 #define USC_SYSIOSTS 0x54 /* sysio/u2s port status */ 58 #define USC_FFBCFG 0x58 /* dsc: ffb config */ 59 #define USC_FFBSTS 0x5c /* dsc: ffb status */ 60 #define USC_MCCTRL0 0x60 /* usc: memory control 0 */ 61 #define USC_MCCTRL1 0x64 /* usc: memory control 1 */ 62 #define USC_CCDIAG 0x70 /* dsc: */ 63 #define USC_CCVEC 0x74 /* dsc: */ 64 #define USC_CCFLT 0x78 /* dsc: */ 65 #define USC_CCPRC 0x7c /* dsc: */ 66 #define USC_MEM0 0x80 /* dsc: mem control 0 */ 67 #define USC_MEM1 0x84 /* dsc: RAS control */ 68 #define USC_MEM2 0x88 /* dsc: CAS_RD control */ 69 #define USC_MEM3 0x8c /* dsc: Bank_Sel control */ 70 #define USC_MEM4 0x90 /* dsc: BMX_Buffer control */ 71 #define USC_MEM5 0x94 /* dsc: CAS_WR control */ 72 #define USC_MEM6 0x98 /* dsc: Phase_Level control */ 73 #define USC_MEM7 0x9c /* dsc: SIMM_Busy_Rd control */ 74 #define USC_MEM8 0xa0 /* dsc: Count_Control */ 75 #define USC_MEM9 0xa4 /* dsc: Refresh control */ 76 #define USC_MEMA 0xa8 /* dsc: Row control */ 77 #define USC_MEMB 0xac /* dsc: guess! */ 78 79 #define USC_CTRL_POR 0x80000000 /* power on reset */ 80 #define USC_CTRL_SFTPOR 0x40000000 /* last reset was soft */ 81 #define USC_CTRL_XIR 0x20000000 /* initiate XIR */ 82 #define USC_CTRL_BPOR 0x10000000 /* last reset was scan */ 83 #define USC_CTRL_BXIR 0x08000000 /* last reset was xir */ 84 #define USC_CTRL_WAKEUP 0x04000000 /* last reset was wakeup */ 85 #define USC_CTRL_FATAL 0x02000000 /* fatal error detect */ 86 #define USC_CTRL_IAP 0x00800000 /* inv parity on addr bus */ 87 #define USC_CTRL_ENWKUP 0x00400000 /* enable wakeup POR */ 88 89 #define USC_ID_JEDEC 0xffff0000 /* JEDEC ID */ 90 #define USC_ID_UPANUM_M 0x0000f000 /* #UPA ports supported mask */ 91 #define USC_ID_UPANUM_S 12 /* #UPA ports supported shift */ 92 #define USC_ID_IMPL_M 0x000000f0 /* implementation # mask */ 93 #define USC_ID_IMPL_S 4 /* implementation # shift */ 94 #define USC_ID_VERS_M 0x0000000f /* version mask */ 95 #define USC_ID_VERS_S 0 /* version shift */ 96 97 #define USC_PCTRL_CLR1 0x00008000 /* clear cntr in SEL1 */ 98 #define USC_PCTRL_SEL1 0x00000f00 /* event source 1 */ 99 #define USC_PCTRL_CLR0 0x00000080 /* clear cntrl in SEL0 */ 100 #define USC_PCTRL_SEL0 0x0000000f /* event source 0 */ 101 102 /* Event sources, counter 0 */ 103 #define SEL0_SYSCK 0x00000000 /* system clock count */ 104 #define SEL0_PRALL 0x00000001 /* prequests, all sources */ 105 #define SEL0_PRP0 0x00000002 /* prequests, proc 0 */ 106 #define SEL0_PRUS 0x00000004 /* prequests, u2s */ 107 #define SEL0_128BUSY 0x00000005 /* # of cycles 128bit UPA busy */ 108 #define SEL0_64BUSY 0x00000006 /* # of cycles 64bit UPA busy */ 109 #define SEL0_PIOSTALL 0x00000007 /* # cycles stalled during PIO */ 110 #define SEL0_MEMREQ 0x00000008 /* # memory requests issued */ 111 #define SEL0_MCBUSY 0x00000009 /* # cycles memory controller busy */ 112 #define SEL0_PENDSTALL 0x0000000a /* # stalls pending xact scbd hit */ 113 #define SEL0_CWMRP0 0x0000000b /* # coherent write miss req, prc0 */ 114 #define SEL0_CWMRP1 0x0000000c /* # coherent write miss req, prc1 */ 115 #define SEL0_CIT 0x0000000d /* # coherent intervene xacts */ 116 #define SEL0_DACT 0x0000000e /* # data transactions from u2s */ 117 #define SEL0_CRXI 0x0000000f /* # coherent read xacts issued */ 118 119 /* Event sources, counter 1 */ 120 #define SEL1_SYSCK 0x00000000 /* system clock count */ 121 #define SEL1_PRALL 0x00000001 /* prequests, all sources */ 122 #define SEL1_PRP0 0x00000002 /* prequests, proc 0 */ 123 #define SEL1_PRUS 0x00000004 /* prequests, u2s */ 124 #define SEL1_RDP0 0x00000005 /* read reqs from P0 */ 125 #define SEL1_CRMP0 0x00000006 /* coherent read misses from P0 */ 126 #define SEL1_PIOP0 0x00000007 /* PIO accesses from P0 */ 127 #define SEL1_MRI 0x00000008 /* memory reqs issued */ 128 #define SEL1_MRC 0x00000009 /* memory reqs complete */ 129 #define SEL1_RDP1 0x0000000a /* read reqs from P1 */ 130 #define SEL1_CRMP1 0x0000000b /* coherent read misses from P1 */ 131 #define SEL1_PIOP1 0x0000000c /* PIO accesses from P1 */ 132 #define SEL1_CWXI 0x0000000d /* coherent write xacts issued */ 133 #define SEL1_DXU 0x0000000e /* # data xacts from u2s */ 134 135 /* Port config (USC_P0CFG, USC_P1CFG, USC_SYSIOCFG, USC_FFBCFG) */ 136 #define USC_PCFG_MD 0x80000000 /* master disable */ 137 #define USC_PCFG_SSLP 0x40000000 /* slave sleep */ 138 #define USC_PCFG_SPRQS 0x0f000000 /* slave prequest queue size */ 139 #define USC_PCFG_SIQS 0x00030000 /* slave interrupt queue size */ 140 #define USC_PCFG_SQEN 0x00008000 /* qualifies writes to SPRQS,SIQS */ 141 #define USC_PCFG_ONER 0x00004000 /* one read */ 142 143 /* Port status (USC_P0STS, USC_P1STS, USC_SYSIOSTS, USC_FFBSTS) */ 144 #define USC_PSTS_FATAL 0x80000000 /* fatal error detected */ 145 #define USC_PSTS_IADDR 0x40000000 /* invalid address */ 146 #define USC_PSTS_IPORT 0x20000000 /* invalid port */ 147 #define USC_PSTS_IPRTY 0x10000000 /* parity error */ 148 #define USC_PSTS_MC0OF 0x08000000 /* master class 0 overflow */ 149 #define USC_PSTS_MC1OF 0x04000000 /* master class 1 overflow */ 150 #define USC_PSTS_MCQ0 0x03800000 /* # reqs before mc0 overflow */ 151 #define USC_PSTS_MC1Q 0x00700000 /* # reqs before mc1 overflow */ 152 153 /* usc: memory control 0 */ 154 #define USC_MC0_REFEN 0x80000000 /* refresh enable */ 155 #define USC_MC0_SIMP 0x0000ff00 /* simms present */ 156 #define USC_MC0_REFI 0x000000ff /* refresh interval */ 157 158 /* usc: memory control 1 */ 159 #define USC_MC1_CSR 0x00001000 /* CAS-to-RAS delay for CBR ref cyc */ 160 #define USC_MC1_WPC1 0x00000c00 /* page cycle 1 write */ 161 #define USC_MC1_RCD 0x00000200 /* RAS-to-CAS delay */ 162 #define USC_MC1_CP 0x00000100 /* CAS precharge */ 163 #define USC_MC1_RP 0x000000c0 /* RAS precharge */ 164 #define USC_MC1_RAS 0x00000030 /* length of RAS for precharge */ 165 #define USC_MC1_PC0 0x0000000c /* page cycle 0 */ 166 #define USC_MC1_PC1 0x00000003 /* page cycle 1 */ 167 168 /* dsc: memory control 0 */ 169 #define USC_MEM0_REFE 0x80000000 /* refresh enable */ 170 #define USC_MEM0_FSME 0x10000000 /* fsm error */ 171 #define USC_MEM0_PPE 0x08000000 /* ping-pong buffer error */ 172 #define USC_MEM0_DPSE 0x04000000 /* data path scheduler error */ 173 #define USC_MEM0_MCE 0x02000000 /* memory controller error */ 174 #define USC_MEM0_MRE 0x01000000 /* missed refresh error */ 175 #define USC_MEM0_RPMC 0x00800000 /* RAS Phi 0 cookie for refresh */ 176 #define USC_MEM0_RWMC 0x00400000 /* RAS Phi 0 cookie for writers */ 177 #define USC_MEM0_SW0 0x001f0000 /* stretch count for first write */ 178 #define USC_MEM0_SP 0x00000f00 /* simm present mask */ 179 #define USC_MEM0_REFI 0x000000ff /* refresh interval */ 180 181 /* cache coherence diagnostic: USC_CCDIAG */ 182 #define USC_CCDIAG_SNP 0xffff0000 /* SRAM address */ 183 #define USC_CCDIAG_DME 0x00008000 /* enable writes to DTAG */ 184 185 /* cache coherence snoop vector: USC_CCVEC */ 186 #define USC_CCVEC_TAG 0x7ff80000 /* tag portion of SRAM data */ 187 #define USC_CCVEC_ST 0x00060000 /* state portion of SRAM data */ 188 #define USC_CCVEC_PAR 0x00010000 /* parity portion of SRAM data */ 189 190 /* cache coherence fault: USC_CCFLT */ 191 #define USC_CCFLT_PERR0 0x80000000 /* dual tag parity error, proc 0 */ 192 #define USC_CCFLT_CERR0 0x40000000 /* coherence error, proc 0 */ 193 #define USC_CCFLT_PERR1 0x20000000 /* dual tag parity error, proc 1 */ 194 #define USC_CCFLT_CERR1 0x10000000 /* coherence error, proc 1 */ 195 #define USC_CCFLT_IDX 0x0fffe000 /* index of fault */ 196 197 /* cache coherence processor index: USC_CCPRC */ 198 #define USC_CCPRC_PIDX 0x7fffffff /* address mask for ports 1 & 2 */ 199