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Searched refs:UVD_CGC_CTRL__SYS_MODE_MASK (Results 1 – 22 of 22) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h449 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro
H A Duvd_3_1_sh_mask.h237 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
H A Duvd_4_0_sh_mask.h60 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L macro
H A Duvd_4_2_sh_mask.h237 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
H A Duvd_5_0_sh_mask.h259 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
H A Duvd_6_0_sh_mask.h261 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c567 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v4_0_3_disable_clock_gating()
639 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v4_0_3_disable_clock_gating_dpg_mode()
694 data |= (UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v1_0.c517 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v1_0_disable_clock_gating()
617 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v1_0_enable_clock_gating()
675 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_0.c536 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_0_disable_clock_gating()
612 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
673 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_0_enable_clock_gating()
H A Dvcn_v4_0.c707 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v4_0_disable_clock_gating()
792 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v4_0_disable_clock_gating_dpg_mode()
850 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v4_0_enable_clock_gating()
H A Dvcn_v2_5.c622 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_5_disable_clock_gating()
699 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
761 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_5_enable_clock_gating()
H A Duvd_v5_0.c696 UVD_CGC_CTRL__SYS_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
H A Dvcn_v3_0.c744 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v3_0_disable_clock_gating()
843 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
902 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v3_0_enable_clock_gating()
H A Duvd_v6_0.c1353 UVD_CGC_CTRL__SYS_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
H A Duvd_v7_0.c1637 UVD_CGC_CTRL__SYS_MODE_MASK |
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h942 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2010 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1961 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3681 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2740 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h118 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h118 #define UVD_CGC_CTRL__SYS_MODE_MASK … macro