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Searched refs:UVD_CGC_CTRL__WCB_MODE_MASK (Results 1 – 22 of 22) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h461 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro
H A Duvd_3_1_sh_mask.h261 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 macro
H A Duvd_4_0_sh_mask.h76 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L macro
H A Duvd_4_2_sh_mask.h261 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 macro
H A Duvd_5_0_sh_mask.h283 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 macro
H A Duvd_6_0_sh_mask.h285 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c576 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v4_0_3_disable_clock_gating()
650 UVD_CGC_CTRL__WCB_MODE_MASK | in vcn_v4_0_3_disable_clock_gating_dpg_mode()
703 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v1_0.c529 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v1_0_disable_clock_gating()
629 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v1_0_enable_clock_gating()
687 UVD_CGC_CTRL__WCB_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_0.c548 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v2_0_disable_clock_gating()
624 UVD_CGC_CTRL__WCB_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
685 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v2_0_enable_clock_gating()
H A Dvcn_v4_0.c719 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v4_0_disable_clock_gating()
804 UVD_CGC_CTRL__WCB_MODE_MASK | in vcn_v4_0_disable_clock_gating_dpg_mode()
862 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v4_0_enable_clock_gating()
H A Dvcn_v2_5.c634 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v2_5_disable_clock_gating()
711 UVD_CGC_CTRL__WCB_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
773 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v2_5_enable_clock_gating()
H A Duvd_v5_0.c708 UVD_CGC_CTRL__WCB_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
H A Dvcn_v3_0.c756 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v3_0_disable_clock_gating()
855 UVD_CGC_CTRL__WCB_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
914 | UVD_CGC_CTRL__WCB_MODE_MASK in vcn_v3_0_enable_clock_gating()
H A Duvd_v6_0.c1365 UVD_CGC_CTRL__WCB_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
H A Duvd_v7_0.c1649 UVD_CGC_CTRL__WCB_MODE_MASK |
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h954 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2022 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1973 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3693 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2752 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h130 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h130 #define UVD_CGC_CTRL__WCB_MODE_MASK … macro