Home
last modified time | relevance | path

Searched refs:UVD_MPC_SET_MUXB0__VARB_3__SHIFT (Results 1 – 19 of 19) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h619 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Duvd_3_1_sh_mask.h500 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
H A Duvd_4_0_sh_mask.h519 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012 macro
H A Duvd_4_2_sh_mask.h504 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
H A Duvd_5_0_sh_mask.h536 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
H A Duvd_6_0_sh_mask.h538 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1126 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_2_5_sh_mask.h2867 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_2_0_0_sh_mask.h2632 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_2_6_0_sh_mask.h2859 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_3_0_0_sh_mask.h3940 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_4_0_0_sh_mask.h4190 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_4_0_3_sh_mask.h4233 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c784 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_3_start_dpg_mode()
1110 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_3_start()
H A Dvcn_v1_0.c845 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v1_0_start_spg_mode()
1028 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_0.c853 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_0_start_dpg_mode()
986 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_0_start()
H A Dvcn_v4_0.c972 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_start_dpg_mode()
1111 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_start()
H A Dvcn_v2_5.c878 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start_dpg_mode()
1032 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start()
H A Dvcn_v3_0.c1001 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v3_0_start_dpg_mode()
1165 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v3_0_start()