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Searched refs:UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h260 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Duvd_5_0_sh_mask.h795 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h552 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2185 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3311 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3856 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2942 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h2870 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h2870 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v1_0.c568 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v1_0_disable_clock_gating()
640 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v1_0_enable_clock_gating()
H A Dvcn_v2_0.c587 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v2_0_disable_clock_gating()
696 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v2_0_enable_clock_gating()
H A Dvcn_v4_0.c757 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v4_0_disable_clock_gating()
873 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v4_0_enable_clock_gating()
H A Dvcn_v2_5.c673 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v2_5_disable_clock_gating()
783 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v2_5_enable_clock_gating()
H A Dvcn_v3_0.c809 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v3_0_disable_clock_gating()
925 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v3_0_enable_clock_gating()