Home
last modified time | relevance | path

Searched refs:UVD_SUVD_CGC_GATE__SCM_H264_MASK (Results 1 – 17 of 17) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Duvd_v6_0.c670 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
703 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1293 UVD_SUVD_CGC_GATE__SCM_H264_MASK | in uvd_v6_0_enable_clock_gating()
H A Dvcn_v4_0_3.c591 | UVD_SUVD_CGC_GATE__SCM_H264_MASK in vcn_v4_0_3_disable_clock_gating()
H A Dvcn_v1_0.c545 | UVD_SUVD_CGC_GATE__SCM_H264_MASK in vcn_v1_0_disable_clock_gating()
H A Dvcn_v2_0.c564 | UVD_SUVD_CGC_GATE__SCM_H264_MASK in vcn_v2_0_disable_clock_gating()
H A Dvcn_v4_0.c734 | UVD_SUVD_CGC_GATE__SCM_H264_MASK in vcn_v4_0_disable_clock_gating()
H A Dvcn_v2_5.c650 | UVD_SUVD_CGC_GATE__SCM_H264_MASK in vcn_v2_5_disable_clock_gating()
H A Dvcn_v3_0.c771 | UVD_SUVD_CGC_GATE__SCM_H264_MASK in vcn_v3_0_disable_clock_gating()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h235 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro
H A Duvd_5_0_sh_mask.h741 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 macro
H A Duvd_6_0_sh_mask.h743 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h463 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro
H A Dvcn_2_5_sh_mask.h2092 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3218 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3763 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2828 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro
H A Dvcn_4_0_0_sh_mask.h1345 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro
H A Dvcn_4_0_3_sh_mask.h1345 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK … macro