| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCallingConv.td | 116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
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| H A D | HexagonRegisterInfo.cpp | 81 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
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| H A D | HexagonRegisterInfo.td | 237 def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>;
257 def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>;
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 232 V8, V9, V10, V11, V12, V13]>>>,
237 V8, V9, V10, V11, V12, V13]>>>,
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| H A D | PPCRegisterInfo.td | 355 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
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| H A D | PPCISelLowering.cpp | 4310 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_64SVR4()
4770 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in needStackSlotPassParameters()
6020 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_64SVR4()
6618 PPC::V10, PPC::V11, PPC::V12, PPC::V13}; in CC_AIX()
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| /openbsd/gnu/llvm/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 109 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 775 APInt V10 = CI10->getValue(); in simplifyX86insertq() local
778 V10 = V10.zextOrTrunc(Length).zextOrTrunc(64).shl(Index); in simplifyX86insertq()
779 APInt Val = V00 | V10; in simplifyX86insertq()
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| /openbsd/gnu/usr.bin/perl/ |
| H A D | README.aix | 43 IBM XL C and IBM XL C/C++ V8, V9, V10, V11
92 5.12.2 |6.1 TL1 SP7 32 bit | XL C/C++ V10 | OK | OK
93 5.12.2 |6.1 TL1 SP7 64 bit | XL C/C++ V10 | OK | OK
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| /openbsd/gnu/usr.bin/perl/Porting/ |
| H A D | checkURL.pl | 453 http://www.li18nux.org/docs/html/CodesetAliasTable-V10.html
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| /openbsd/gnu/llvm/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 100 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 588 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, in DecodeHvxVRRegisterClass()
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstructions.td | 2151 defm : SI_INDIRECT_Pattern <v10f32, f32, "V10">;
2161 defm : SI_INDIRECT_Pattern <v10i32, i32, "V10">;
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11915 RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
13642 .Case("{v10}", RISCV::V10) in getRegForInlineAsmConstraint()
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