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Searched refs:VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK (Results 1 – 19 of 19) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h9613 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L macro
H A Ddce_8_0_sh_mask.h11141 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 macro
H A Ddce_10_0_sh_mask.h11527 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 macro
H A Ddce_11_0_sh_mask.h11339 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 macro
H A Ddce_11_2_sh_mask.h12593 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 macro
H A Ddce_12_0_sh_mask.h2166 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h203 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_1_0_sh_mask.h1716 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_2_1_0_sh_mask.h217 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h614 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4401 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_1_2_sh_mask.h7270 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5100 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7755 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_1_6_sh_mask.h7921 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h216 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h216 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h197 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4400 #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … macro