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Searched refs:VGPR0 (Results 1 – 12 of 12) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp91 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
92 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
93 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
94 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
H A DAMDGPUCallingConv.td33 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
47 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
80 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
113 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
187 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
199 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
H A DGCNNSAReassign.cpp148 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
150 for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) { in scavengeRegs()
H A DSIInsertWaitcnts.cpp84 unsigned VGPR0; member
506 assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL); in getRegInterval()
507 Result.first = Reg - Encoding.VGPR0; in getRegInterval()
1794 Encoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction()
1795 Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1; in runOnMachineFunction()
H A DGCNHazardRecognizer.cpp1779 if (!TRI.isVGPR(MRI, AmtReg) || ((AmtReg - AMDGPU::VGPR0) & 7) != 7) in fixShift64HighRegBug()
1793 static_assert(AMDGPU::VGPR0 + 1 == AMDGPU::VGPR1); in fixShift64HighRegBug()
H A DAMDGPUCallLowering.cpp685 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
H A DSOPInstructions.td845 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
H A DSIRegisterInfo.cpp183 TmpVGPR = AMDGPU::VGPR0; in prepare()
H A DSIISelLowering.cpp1927 Register Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs()
1939 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1953 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2437 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
/openbsd/gnu/llvm/llvm/docs/
H A DAMDGPUUsage.rst1862 1536-1791 VGPR0-VGPR255 32*32 Vector General Purpose Registers
1874 2560-2815 VGPR0-VGPR255 64*32 Vector General Purpose Registers
4743 for enabled registers are dense starting at VGPR0: the first enabled register is
4744 VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
4754 specifies *Packed work-item IDs*, the initial value of VGPR0 register is used
13339 ``VGPR0``:
13518 6. VGPR0-31 and SGPR4-29 are used to pass function input arguments as described
13566 1. VGPR0-31 and SGPR4-29 are used to pass function result arguments as
13753 * VGPR arguments are assigned to consecutive VGPRs starting at VGPR0 up to
/openbsd/gnu/llvm/llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/
H A DAMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md935 DW_OP_regx VGPR0
989 DW_OP_regx VGPR0
1004 The DW_OP_regx VGPR0 pushes a location description for the first register.
1072 DW_OP_regx VGPR0
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4396 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4487 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()