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Searched refs:VGPR32 (Results 1 – 4 of 4) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h34 VGPR32, enumerator
52 return Value[AGPR32] ? alignTo(Value[VGPR32], 4) + Value[AGPR32] in getVGPRNum()
53 : Value[VGPR32] + Value[AGPR32]; in getVGPRNum()
55 return std::max(Value[VGPR32], Value[AGPR32]); in getVGPRNum()
H A DGCNRegPressure.cpp47 : (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
66 case VGPR32: in inc()
76 Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] += in inc()
140 OS << "VGPRs: " << RP.Value[GCNRegPressure::VGPR32] << ' ' in print()
H A DAMDGPUCallingConv.td51 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
84 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
117 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4385 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign() local
4396 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4482 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS() local
4487 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()