1 /* $OpenBSD: if_vmxreg.h,v 1.10 2024/06/07 08:44:25 jan Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Tsubai Masanari 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 enum UPT1_TxStats { 20 UPT1_TxStat_TSO_packets, 21 UPT1_TxStat_TSO_bytes, 22 UPT1_TxStat_ucast_packets, 23 UPT1_TxStat_ucast_bytes, 24 UPT1_TxStat_mcast_packets, 25 UPT1_TxStat_mcast_bytes, 26 UPT1_TxStat_bcast_packets, 27 UPT1_TxStat_bcast_bytes, 28 UPT1_TxStat_error, 29 UPT1_TxStat_discard, 30 31 UPT1_TxStats_count, 32 } __packed; 33 34 enum UPT1_RxStats { 35 UPT1_RXStat_LRO_packets, 36 UPT1_RXStat_LRO_bytes, 37 UPT1_RXStat_ucast_packets, 38 UPT1_RXStat_ucast_bytes, 39 UPT1_RXStat_mcast_packets, 40 UPT1_RXStat_mcast_bytes, 41 UPT1_RXStat_bcast_packets, 42 UPT1_RXStat_bcast_bytes, 43 UPT1_RXStat_nobuffer, 44 UPT1_RXStat_error, 45 46 UPT1_RxStats_count, 47 } __packed; 48 49 /* interrupt moderation levels */ 50 #define UPT1_IMOD_NONE 0 /* no moderation */ 51 #define UPT1_IMOD_HIGHEST 7 /* least interrupts */ 52 #define UPT1_IMOD_ADAPTIVE 8 /* adaptive interrupt moderation */ 53 54 /* hardware features */ 55 #define UPT1_F_CSUM 0x0001 /* Rx checksum verification */ 56 #define UPT1_F_RSS 0x0002 /* receive side scaling */ 57 #define UPT1_F_VLAN 0x0004 /* VLAN tag stripping */ 58 #define UPT1_F_LRO 0x0008 /* large receive offloading */ 59 60 #define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8) /* interrupt mask */ 61 #define VMXNET3_BAR0_TXH(q) (0x600 + (q) * 8) /* Tx head */ 62 #define VMXNET3_BAR0_RXH1(q) (0x800 + (q) * 8) /* ring1 Rx head */ 63 #define VMXNET3_BAR0_RXH2(q) (0xa00 + (q) * 8) /* ring2 Rx head */ 64 #define VMXNET3_BAR1_VRRS 0x000 /* VMXNET3 revision report selection */ 65 #define VMXNET3_BAR1_UVRS 0x008 /* UPT version report selection */ 66 #define VMXNET3_BAR1_DSL 0x010 /* driver shared address low */ 67 #define VMXNET3_BAR1_DSH 0x018 /* driver shared address high */ 68 #define VMXNET3_BAR1_CMD 0x020 /* command */ 69 #define VMXNET3_BAR1_MACL 0x028 /* MAC address low */ 70 #define VMXNET3_BAR1_MACH 0x030 /* MAC address high */ 71 #define VMXNET3_BAR1_INTR 0x038 /* interrupt status */ 72 #define VMXNET3_BAR1_EVENT 0x040 /* event status */ 73 74 #define VMXNET3_CMD_ENABLE 0xcafe0000 /* enable VMXNET3 */ 75 #define VMXNET3_CMD_DISABLE 0xcafe0001 /* disable VMXNET3 */ 76 #define VMXNET3_CMD_RESET 0xcafe0002 /* reset device */ 77 #define VMXNET3_CMD_SET_RXMODE 0xcafe0003 /* set interface flags */ 78 #define VMXNET3_CMD_SET_FILTER 0xcafe0004 /* set address filter */ 79 #define VMXNET3_CMD_SET_FEATURE 0xcafe0009 /* set features */ 80 #define VMXNET3_CMD_GET_STATUS 0xf00d0000 /* get queue errors */ 81 #define VMXNET3_CMD_GET_STATS 0xf00d0001 82 #define VMXNET3_CMD_GET_LINK 0xf00d0002 /* get link status */ 83 #define VMXNET3_CMD_GET_MACL 0xf00d0003 84 #define VMXNET3_CMD_GET_MACH 0xf00d0004 85 #define VMXNET3_CMD_GET_INTRCFG 0xf00d0008 /* get interrupt config */ 86 #define VMXNET3_INTRCFG_TYPE_SHIFT 0 87 #define VMXNET3_INTRCFG_TYPE_MASK (0x3 << VMXNET3_INTRCFG_TYPE_SHIFT) 88 #define VMXNET3_INTRCFG_TYPE_AUTO (0x0 << VMXNET3_INTRCFG_TYPE_SHIFT) 89 #define VMXNET3_INTRCFG_TYPE_INTX (0x1 << VMXNET3_INTRCFG_TYPE_SHIFT) 90 #define VMXNET3_INTRCFG_TYPE_MSI (0x2 << VMXNET3_INTRCFG_TYPE_SHIFT) 91 #define VMXNET3_INTRCFG_TYPE_MSIX (0x3 << VMXNET3_INTRCFG_TYPE_SHIFT) 92 #define VMXNET3_INTRCFG_MODE_SHIFT 2 93 #define VMXNET3_INTRCFG_MODE_MASK (0x3 << VMXNET3_INTRCFG_MODE_SHIFT) 94 #define VMXNET3_INTRCFG_MODE_AUTO (0x0 << VMXNET3_INTRCFG_MODE_SHIFT) 95 #define VMXNET3_INTRCFG_MODE_ACTIVE (0x1 << VMXNET3_INTRCFG_MODE_SHIFT) 96 #define VMXNET3_INTRCFG_MODE_LAZY (0x2 << VMXNET3_INTRCFG_MODE_SHIFT) 97 98 #define VMXNET3_DMADESC_ALIGN 128 99 100 /* All descriptors are in little-endian format. */ 101 struct vmxnet3_txdesc { 102 u_int64_t tx_addr; 103 104 u_int32_t tx_word2; 105 #define VMXNET3_TX_LEN_M 0x00003fff 106 #define VMXNET3_TX_LEN_S 0 107 #define VMXNET3_TX_GEN_M 0x00000001U /* generation */ 108 #define VMXNET3_TX_GEN_S 14 109 #define VMXNET3_TX_RES0 0x00008000 110 #define VMXNET3_TX_DTYPE_M 0x00000001 /* descriptor type */ 111 #define VMXNET3_TX_DTYPE_S 16 /* descriptor type */ 112 #define VMXNET3_TX_RES1 0x00000002 113 #define VMXNET3_TX_OP_M 0x00003fff /* offloading position */ 114 #define VMXNET3_TX_OP_S 18 115 116 u_int32_t tx_word3; 117 #define VMXNET3_TX_HLEN_M 0x000003ff /* header len */ 118 #define VMXNET3_TX_HLEN_S 0 119 #define VMXNET3_TX_OM_M 0x00000003 /* offloading mode */ 120 #define VMXNET3_TX_OM_S 10 121 #define VMXNET3_TX_EOP 0x00001000 /* end of packet */ 122 #define VMXNET3_TX_COMPREQ 0x00002000 /* completion request */ 123 #define VMXNET3_TX_RES2 0x00004000 124 #define VMXNET3_TX_VTAG_MODE 0x00008000 /* VLAN tag insertion mode */ 125 #define VMXNET3_TX_VLANTAG_M 0x0000ffff 126 #define VMXNET3_TX_VLANTAG_S 16 127 } __packed; 128 129 /* offloading modes */ 130 #define VMXNET3_OM_NONE 0 131 #define VMXNET3_OM_CSUM 2 132 #define VMXNET3_OM_TSO 3 133 134 struct vmxnet3_txcompdesc { 135 u_int32_t txc_word0; 136 #define VMXNET3_TXC_EOPIDX_M 0x00000fff /* eop index in Tx ring */ 137 #define VMXNET3_TXC_EOPIDX_S 0 138 #define VMXNET3_TXC_RES0_M 0x000fffff 139 #define VMXNET3_TXC_RES0_S 12 140 141 u_int32_t txc_word1; 142 u_int32_t txc_word2; 143 144 u_int32_t txc_word3; 145 #define VMXNET3_TXC_RES2_M 0x00ffffff 146 #define VMXNET3_TXC_TYPE_M 0x0000007f 147 #define VMXNET3_TXC_TYPE_S 24 148 #define VMXNET3_TXC_GEN_M 0x00000001U 149 #define VMXNET3_TXC_GEN_S 31 150 } __packed; 151 152 struct vmxnet3_rxdesc { 153 u_int64_t rx_addr; 154 155 u_int32_t rx_word2; 156 #define VMXNET3_RX_LEN_M 0x00003fff 157 #define VMXNET3_RX_LEN_S 0 158 #define VMXNET3_RX_BTYPE_M 0x00000001 /* buffer type */ 159 #define VMXNET3_RX_BTYPE_S 14 160 #define VMXNET3_RX_DTYPE_M 0x00000001 /* descriptor type */ 161 #define VMXNET3_RX_DTYPE_S 15 162 #define VMXNET3_RX_RES0_M 0x00007fff 163 #define VMXNET3_RX_RES0_S 16 164 #define VMXNET3_RX_GEN_M 0x00000001U 165 #define VMXNET3_RX_GEN_S 31 166 167 u_int32_t rx_word3; 168 } __packed; 169 170 /* buffer types */ 171 #define VMXNET3_BTYPE_HEAD 0 /* head only */ 172 #define VMXNET3_BTYPE_BODY 1 /* body only */ 173 174 struct vmxnet3_rxcompdesc { 175 u_int32_t rxc_word0; 176 #define VMXNET3_RXC_IDX_M 0x00000fff /* Rx descriptor index */ 177 #define VMXNET3_RXC_IDX_S 0 178 #define VMXNET3_RXC_RES0_M 0x00000003 179 #define VMXNET3_RXC_RES0_S 12 180 #define VMXNET3_RXC_EOP 0x00004000 /* end of packet */ 181 #define VMXNET3_RXC_SOP 0x00008000 /* start of packet */ 182 #define VMXNET3_RXC_QID_M 0x000003ff 183 #define VMXNET3_RXC_QID_S 16 184 #define VMXNET3_RXC_RSSTYPE_M 0x0000000f 185 #define VMXNET3_RXC_RSSTYPE_S 26 186 #define VMXNET3_RXC_RSSTYPE_NONE 0 187 #define VMXNET3_RXC_NOCSUM 0x40000000 /* no checksum calculated */ 188 #define VMXNET3_RXC_RES1 0x80000000 189 190 u_int32_t rxc_word1; 191 #define VMXNET3_RXC_RSSHASH_M 0xffffffff /* RSS hash value */ 192 #define VMXNET3_RXC_RSSHASH_S 0 193 #define VMXNET3_RXC_SEG_CNT_M 0x000000ff /* No. of seg. in LRO pkt */ 194 195 u_int32_t rxc_word2; 196 #define VMXNET3_RXC_LEN_M 0x00003fff 197 #define VMXNET3_RXC_LEN_S 0 198 #define VMXNET3_RXC_ERROR 0x00004000 199 #define VMXNET3_RXC_VLAN 0x00008000 /* 802.1Q VLAN frame */ 200 #define VMXNET3_RXC_VLANTAG_M 0x0000ffff /* VLAN tag */ 201 #define VMXNET3_RXC_VLANTAG_S 16 202 203 u_int32_t rxc_word3; 204 #define VMXNET3_RXC_CSUM_M 0x0000ffff /* TCP/UDP checksum */ 205 #define VMXNET3_RXC_CSUM_S 16 206 #define VMXNET3_RXC_CSUM_OK 0x00010000 /* TCP/UDP checksum ok */ 207 #define VMXNET3_RXC_UDP 0x00020000 208 #define VMXNET3_RXC_TCP 0x00040000 209 #define VMXNET3_RXC_IPSUM_OK 0x00080000 /* IP checksum ok */ 210 #define VMXNET3_RXC_IPV6 0x00100000 211 #define VMXNET3_RXC_IPV4 0x00200000 212 #define VMXNET3_RXC_FRAGMENT 0x00400000 /* IP fragment */ 213 #define VMXNET3_RXC_FCS 0x00800000 /* frame CRC correct */ 214 #define VMXNET3_RXC_TYPE_M 0x7f000000 215 #define VMXNET3_RXC_TYPE_S 24 216 #define VMXNET3_RXC_GEN_M 0x00000001U 217 #define VMXNET3_RXC_GEN_S 31 218 } __packed; 219 220 #define VMXNET3_REV1_MAGIC 0xbabefee1 221 222 #define VMXNET3_GOS_UNKNOWN 0x00 223 #define VMXNET3_GOS_LINUX 0x04 224 #define VMXNET3_GOS_WINDOWS 0x08 225 #define VMXNET3_GOS_SOLARIS 0x0c 226 #define VMXNET3_GOS_FREEBSD 0x10 227 #define VMXNET3_GOS_PXE 0x14 228 229 #define VMXNET3_GOS_32BIT 0x01 230 #define VMXNET3_GOS_64BIT 0x02 231 232 #define VMXNET3_MAX_TX_QUEUES 8 233 #define VMXNET3_MAX_RX_QUEUES 16 234 #define VMXNET3_MAX_INTRS (VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1) 235 #define VMXNET3_NINTR 1 236 237 #define VMXNET3_ICTRL_DISABLE_ALL 0x01 238 239 #define VMXNET3_RXMODE_UCAST 0x01 240 #define VMXNET3_RXMODE_MCAST 0x02 241 #define VMXNET3_RXMODE_BCAST 0x04 242 #define VMXNET3_RXMODE_ALLMULTI 0x08 243 #define VMXNET3_RXMODE_PROMISC 0x10 244 245 #define VMXNET3_EVENT_RQERROR 0x01 246 #define VMXNET3_EVENT_TQERROR 0x02 247 #define VMXNET3_EVENT_LINK 0x04 248 #define VMXNET3_EVENT_DIC 0x08 249 #define VMXNET3_EVENT_DEBUG 0x10 250 251 #define VMXNET3_MAX_MTU 9000 252 #define VMXNET3_MIN_MTU 60 253 254 struct vmxnet3_driver_shared { 255 u_int32_t magic; 256 u_int32_t pad1; 257 258 u_int32_t version; /* driver version */ 259 u_int32_t guest; /* guest OS */ 260 u_int32_t vmxnet3_revision; /* supported VMXNET3 revision */ 261 u_int32_t upt_version; /* supported UPT version */ 262 u_int64_t upt_features; 263 u_int64_t driver_data; 264 u_int64_t queue_shared; 265 u_int32_t driver_data_len; 266 u_int32_t queue_shared_len; 267 u_int32_t mtu; 268 u_int16_t nrxsg_max; 269 u_int8_t ntxqueue; 270 u_int8_t nrxqueue; 271 u_int32_t reserved1[4]; 272 273 /* interrupt control */ 274 u_int8_t automask; 275 u_int8_t nintr; 276 u_int8_t evintr; 277 u_int8_t modlevel[VMXNET3_MAX_INTRS]; 278 u_int32_t ictrl; 279 u_int32_t reserved2[2]; 280 281 /* receive filter parameters */ 282 u_int32_t rxmode; 283 u_int16_t mcast_tablelen; 284 u_int16_t pad2; 285 u_int64_t mcast_table; 286 u_int32_t vlan_filter[4096 / 32]; 287 288 struct { 289 u_int32_t version; 290 u_int32_t len; 291 u_int64_t paddr; 292 } rss, pm, plugin; 293 294 u_int32_t event; 295 u_int32_t reserved3[5]; 296 } __packed; 297 298 struct vmxnet3_txq_shared { 299 u_int32_t npending; 300 u_int32_t intr_threshold; 301 u_int64_t reserved1; 302 303 u_int64_t cmd_ring; 304 u_int64_t data_ring; 305 u_int64_t comp_ring; 306 u_int64_t driver_data; 307 u_int64_t reserved2; 308 u_int32_t cmd_ring_len; 309 u_int32_t data_ring_len; 310 u_int32_t comp_ring_len; 311 u_int32_t driver_data_len; 312 u_int8_t intr_idx; 313 u_int8_t pad1[7]; 314 315 u_int8_t stopped; 316 u_int8_t pad2[3]; 317 u_int32_t error; 318 319 uint64_t stats[UPT1_TxStats_count]; 320 321 u_int8_t pad3[88]; 322 } __packed; 323 324 struct vmxnet3_rxq_shared { 325 u_int8_t update_rxhead; 326 u_int8_t pad1[7]; 327 u_int64_t reserved1; 328 329 u_int64_t cmd_ring[2]; 330 u_int64_t comp_ring; 331 u_int64_t driver_data; 332 u_int64_t reserved2; 333 u_int32_t cmd_ring_len[2]; 334 u_int32_t comp_ring_len; 335 u_int32_t driver_data_len; 336 u_int8_t intr_idx; 337 u_int8_t pad2[7]; 338 339 u_int8_t stopped; 340 u_int8_t pad3[3]; 341 u_int32_t error; 342 343 uint64_t stats[UPT1_RxStats_count]; 344 345 u_int8_t pad4[88]; 346 } __packed; 347 348 #define UPT1_RSS_MAX_KEY_SIZE 40 349 #define UPT1_RSS_MAX_IND_TABLE_SIZE 128 350 351 struct vmxnet3_upt1_rss_conf { 352 u_int16_t hash_type; 353 #define UPT1_RSS_HASH_TYPE_NONE 0 354 #define UPT1_RSS_HASH_TYPE_IPV4 1 355 #define UPT1_RSS_HASH_TYPE_TCP_IPV4 2 356 #define UPT1_RSS_HASH_TYPE_IPV6 4 357 #define UPT1_RSS_HASH_TYPE_TCP_IPV6 8 358 u_int16_t hash_func; 359 #define UPT1_RSS_HASH_FUNC_TOEPLITZ 1 360 u_int16_t hash_key_size; 361 u_int16_t ind_table_size; 362 u_int8_t hash_key[UPT1_RSS_MAX_KEY_SIZE]; 363 u_int8_t ind_table[UPT1_RSS_MAX_IND_TABLE_SIZE]; 364 } __packed; 365