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Searched refs:WR2_INTR_0 (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/arch/luna88k/dev/
H A Dsioreg.h80 #define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */ macro
/openbsd/sys/arch/luna88k/stand/boot/
H A Dsioreg.h128 #define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */ macro