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Searched refs:WR3 (Results 1 – 7 of 7) sorted by relevance

/openbsd/sys/arch/luna88k/dev/
H A Dsiotty.c152 setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]); in siotty_attach()
384 sc->sc_wr[WR3] &= 0x3f; in sioparam()
388 sc->sc_wr[WR3] |= WR3_RX7BIT; sc->sc_wr[WR5] |= WR5_TX7BIT; in sioparam()
391 sc->sc_wr[WR3] |= WR3_RX8BIT; sc->sc_wr[WR5] |= WR5_TX8BIT; in sioparam()
404 setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]); in sioparam()
670 setsioreg(sio, WR3, ch0_regs[WR3]); in syscnattach()
H A Dsioreg.h45 #define WR3 0x03 macro
H A Dlunaws.c175 setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]); in wsattach()
/openbsd/sys/arch/luna88k/stand/boot/
H A Dsio.c211 sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */ in sioinit()
220 sioreg(REG(1, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */ in sioinit()
H A Dsioreg.h93 #define WR3 0x03 macro
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp626 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, in DecodeHvxWRRegisterClass()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td255 def WR3 : Rd< 7, "v6:7", [V6, V7, VFR3]>, DwarfRegNum<[164]>;