1 /* $OpenBSD: xlreg.h,v 1.29 2014/07/08 05:35:18 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_xlreg.h,v 1.26 2000/08/28 20:40:03 wpaul Exp $ 35 */ 36 37 #define XL_EE_READ 0x0080 /* read, 5 bit address */ 38 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */ 39 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 40 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 41 #define XL_EE_EWEN 0x0030 /* erase, no data needed */ 42 #define XL_EE_BUSY 0x8000 43 44 #define XL_EE_EADDR0 0x00 /* station address, first word */ 45 #define XL_EE_EADDR1 0x01 /* station address, next word, */ 46 #define XL_EE_EADDR2 0x02 /* station address, last word */ 47 #define XL_EE_PRODID 0x03 /* product ID code */ 48 #define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 49 #define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 50 #define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 51 #define XL_EE_MFG_ID 0x07 52 #define XL_EE_PCI_PARM 0x08 53 #define XL_EE_ROM_ONFO 0x09 54 #define XL_EE_OEM_ADR0 0x0A 55 #define XL_EE_OEM_ADR1 0x0B 56 #define XL_EE_OEM_ADR2 0x0C 57 #define XL_EE_SOFTINFO1 0x0D 58 #define XL_EE_COMPAT 0x0E 59 #define XL_EE_SOFTINFO2 0x0F 60 #define XL_EE_CAPS 0x10 /* capabilities word */ 61 #define XL_EE_RSVD0 0x11 62 #define XL_EE_ICFG_0 0x12 63 #define XL_EE_ICFG_1 0x13 64 #define XL_EE_RSVD1 0x14 65 #define XL_EE_SOFTINFO3 0x15 66 #define XL_EE_RSVD_2 0x16 67 68 /* 69 * Bits in the capabilities word 70 */ 71 #define XL_CAPS_PNP 0x0001 72 #define XL_CAPS_FULL_DUPLEX 0x0002 73 #define XL_CAPS_LARGE_PKTS 0x0004 74 #define XL_CAPS_SLAVE_DMA 0x0008 75 #define XL_CAPS_SECOND_DMA 0x0010 76 #define XL_CAPS_FULL_BM 0x0020 77 #define XL_CAPS_FRAG_BM 0x0040 78 #define XL_CAPS_CRC_PASSTHRU 0x0080 79 #define XL_CAPS_TXDONE 0x0100 80 #define XL_CAPS_NO_TXLENGTH 0x0200 81 #define XL_CAPS_RX_REPEAT 0x0400 82 #define XL_CAPS_SNOOPING 0x0800 83 #define XL_CAPS_100MBPS 0x1000 84 #define XL_CAPS_PWRMGMT 0x2000 85 86 #define XL_PACKET_SIZE 1540 87 88 #define XL_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 89 90 /* 91 * Register layouts. 92 */ 93 #define XL_COMMAND 0x0E 94 #define XL_STATUS 0x0E 95 96 #define XL_TX_STATUS 0x1B 97 #define XL_TX_FREE 0x1C 98 #define XL_DMACTL 0x20 99 #define XL_DOWNLIST_PTR 0x24 100 #define XL_DOWN_POLL 0x2D /* 3c90xB only */ 101 #define XL_TX_FREETHRESH 0x2F 102 #define XL_UPLIST_PTR 0x38 103 #define XL_UPLIST_STATUS 0x30 104 #define XL_UP_POLL 0x3D /* 3c90xB only */ 105 106 #define XL_PKTSTAT_UP_STALLED 0x00002000 107 #define XL_PKTSTAT_UP_ERROR 0x00004000 108 #define XL_PKTSTAT_UP_CMPLT 0x00008000 109 110 #define XL_DMACTL_DN_CMPLT_REQ 0x00000002 111 #define XL_DMACTL_DOWN_STALLED 0x00000004 112 #define XL_DMACTL_UP_CMPLT 0x00000008 113 #define XL_DMACTL_DOWN_CMPLT 0x00000010 114 #define XL_DMACTL_UP_RX_EARLY 0x00000020 115 #define XL_DMACTL_ARM_COUNTDOWN 0x00000040 116 #define XL_DMACTL_DOWN_INPROG 0x00000080 117 #define XL_DMACTL_COUNTER_SPEED 0x00000100 118 #define XL_DMACTL_DOWNDOWN_MODE 0x00000200 119 #define XL_DMACTL_TARGET_ABORT 0x40000000 120 #define XL_DMACTL_MASTER_ABORT 0x80000000 121 122 /* 123 * Command codes. Some command codes require that we wait for 124 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 125 */ 126 #define XL_CMD_RESET 0x0000 /* mustwait */ 127 #define XL_CMD_WINSEL 0x0800 128 #define XL_CMD_COAX_START 0x1000 129 #define XL_CMD_RX_DISABLE 0x1800 130 #define XL_CMD_RX_ENABLE 0x2000 131 #define XL_CMD_RX_RESET 0x2800 /* mustwait */ 132 #define XL_CMD_UP_STALL 0x3000 /* mustwait */ 133 #define XL_CMD_UP_UNSTALL 0x3001 134 #define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 135 #define XL_CMD_DOWN_UNSTALL 0x3003 136 #define XL_CMD_RX_DISCARD 0x4000 137 #define XL_CMD_TX_ENABLE 0x4800 138 #define XL_CMD_TX_DISABLE 0x5000 139 #define XL_CMD_TX_RESET 0x5800 /* mustwait */ 140 #define XL_CMD_INTR_FAKE 0x6000 141 #define XL_CMD_INTR_ACK 0x6800 142 #define XL_CMD_INTR_ENB 0x7000 143 #define XL_CMD_STAT_ENB 0x7800 144 #define XL_CMD_RX_SET_FILT 0x8000 145 #define XL_CMD_RX_SET_THRESH 0x8800 146 #define XL_CMD_TX_SET_THRESH 0x9000 147 #define XL_CMD_TX_SET_START 0x9800 148 #define XL_CMD_DMA_UP 0xA000 149 #define XL_CMD_DMA_STOP 0xA001 150 #define XL_CMD_STATS_ENABLE 0xA800 151 #define XL_CMD_STATS_DISABLE 0xB000 152 #define XL_CMD_COAX_STOP 0xB800 153 154 #define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 155 #define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 156 157 #define XL_HASH_SET 0x0400 158 #define XL_HASHFILT_SIZE 256 159 160 /* 161 * status codes 162 * Note that bits 15 to 13 indicate the currently visible register window 163 * which may be anything from 0 to 7. 164 */ 165 #define XL_STAT_INTLATCH 0x0001 /* 0 */ 166 #define XL_STAT_ADFAIL 0x0002 /* 1 */ 167 #define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 168 #define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 169 #define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 170 #define XL_STAT_RX_EARLY 0x0020 /* 5 */ 171 #define XL_STAT_INTREQ 0x0040 /* 6 */ 172 #define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 173 #define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 174 #define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 175 #define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 176 #define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 177 #define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 178 #define XL_STAT_CMDBUSY 0x1000 /* 12 */ 179 180 /* 181 * Interrupts we normally want enabled. 182 */ 183 #define XL_INTRS \ 184 (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 185 XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 186 187 /* 188 * Window 0 registers 189 */ 190 #define XL_W0_EE_DATA 0x0C 191 #define XL_W0_EE_CMD 0x0A 192 #define XL_W0_RSRC_CFG 0x08 193 #define XL_W0_ADDR_CFG 0x06 194 #define XL_W0_CFG_CTRL 0x04 195 196 #define XL_W0_PROD_ID 0x02 197 #define XL_W0_MFG_ID 0x00 198 199 /* 200 * Window 1 201 */ 202 203 #define XL_W1_TX_FIFO 0x10 204 205 #define XL_W1_FREE_TX 0x0C 206 #define XL_W1_TX_STATUS 0x0B 207 #define XL_W1_TX_TIMER 0x0A 208 #define XL_W1_RX_STATUS 0x08 209 #define XL_W1_RX_FIFO 0x00 210 211 /* 212 * RX status codes 213 */ 214 #define XL_RXSTATUS_OVERRUN 0x01 215 #define XL_RXSTATUS_RUNT 0x02 216 #define XL_RXSTATUS_ALIGN 0x04 217 #define XL_RXSTATUS_CRC 0x08 218 #define XL_RXSTATUS_OVERSIZE 0x10 219 #define XL_RXSTATUS_DRIBBLE 0x20 220 221 /* 222 * TX status codes 223 */ 224 #define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 225 #define XL_TXSTATUS_OVERFLOW 0x04 226 #define XL_TXSTATUS_MAXCOLS 0x08 227 #define XL_TXSTATUS_UNDERRUN 0x10 228 #define XL_TXSTATUS_JABBER 0x20 229 #define XL_TXSTATUS_INTREQ 0x40 230 #define XL_TXSTATUS_COMPLETE 0x80 231 232 /* 233 * Window 2 234 */ 235 #define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 236 #define XL_W2_STATION_MASK_HI 0x0A 237 #define XL_W2_STATION_MASK_MID 0x08 238 #define XL_W2_STATION_MASK_LO 0x06 239 #define XL_W2_STATION_ADDR_HI 0x04 240 #define XL_W2_STATION_ADDR_MID 0x02 241 #define XL_W2_STATION_ADDR_LO 0x00 242 243 #define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 244 #define XL_RESETOPT_D3RESETDIS 0x0008 245 #define XL_RESETOPT_DISADVFD 0x0010 246 #define XL_RESETOPT_DISADV100 0x0020 247 #define XL_RESETOPT_DISAUTONEG 0x0040 248 #define XL_RESETOPT_DEBUGMODE 0x0080 249 #define XL_RESETOPT_FASTAUTO 0x0100 250 #define XL_RESETOPT_FASTEE 0x0200 251 #define XL_RESETOPT_FORCEDCONF 0x0400 252 #define XL_RESETOPT_TESTPDTPDR 0x0800 253 #define XL_RESETOPT_TEST100TX 0x1000 254 #define XL_RESETOPT_TEST100RX 0x2000 255 256 #define XL_RESETOPT_INVERT_LED 0x0010 257 #define XL_RESETOPT_INVERT_MII 0x4000 258 259 /* 260 * Window 3 (fifo management) 261 */ 262 #define XL_W3_INTERNAL_CFG 0x00 263 #define XL_W3_MAXPKTSIZE 0x04 /* 3C905B only */ 264 #define XL_W3_RESET_OPT 0x08 265 #define XL_W3_FREE_TX 0x0C 266 #define XL_W3_FREE_RX 0x0A 267 #define XL_W3_MAC_CTRL 0x06 268 269 #define XL_ICFG_CONNECTOR_MASK 0x00F00000 270 #define XL_ICFG_CONNECTOR_BITS 20 271 272 #define XL_ICFG_RAMSIZE_MASK 0x00000007 273 #define XL_ICFG_RAMWIDTH 0x00000008 274 #define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 275 #define XL_ICFG_DISABLE_BASSD 0x00000100 276 #define XL_ICFG_RAMLOC 0x00000200 277 #define XL_ICFG_RAMPART (0x00010000|0x00020000) 278 #define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 279 #define XL_ICFG_AUTOSEL 0x01000000 280 281 #define XL_XCVR_10BT 0x00 282 #define XL_XCVR_AUI 0x01 283 #define XL_XCVR_RSVD_0 0x02 284 #define XL_XCVR_COAX 0x03 285 #define XL_XCVR_100BTX 0x04 286 #define XL_XCVR_100BFX 0x05 287 #define XL_XCVR_MII 0x06 288 #define XL_XCVR_RSVD_1 0x07 289 #define XL_XCVR_AUTO 0x08 /* 3c905B only */ 290 #define XL_XCVR_NWAY 0x09 /* 3CCFE575CT CardBus */ 291 292 #define XL_MACCTRL_DEFER_EXT_END 0x0001 293 #define XL_MACCTRL_DEFER_0 0x0002 294 #define XL_MACCTRL_DEFER_1 0x0004 295 #define XL_MACCTRL_DEFER_2 0x0008 296 #define XL_MACCTRL_DEFER_3 0x0010 297 #define XL_MACCTRL_DUPLEX 0x0020 298 #define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 299 #define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 300 #define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 301 #define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 302 303 /* 304 * The 'reset options' register contains power-on reset values 305 * loaded from the EEPROM. This includes the supported media 306 * types on the card. It is also known as the media options register. 307 */ 308 #define XL_W3_MEDIA_OPT 0x08 309 310 #define XL_MEDIAOPT_BT4 0x0001 /* MII */ 311 #define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 312 #define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 313 #define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 314 #define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 315 #define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 316 #define XL_MEDIAOPT_MII 0x0040 /* MII */ 317 #define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 318 319 #define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 320 #define XL_MEDIAOPT_MASK 0x01FF 321 322 /* 323 * Window 4 (diagnostics) 324 */ 325 #define XL_W4_UPPERBYTESOK 0x0D 326 #define XL_W4_BADSSD 0x0C 327 #define XL_W4_MEDIA_STATUS 0x0A 328 #define XL_W4_PHY_MGMT 0x08 329 #define XL_W4_NET_DIAG 0x06 330 #define XL_W4_FIFO_DIAG 0x04 331 #define XL_W4_VCO_DIAG 0x02 332 333 #define XL_W4_CTRLR_STAT 0x08 334 #define XL_W4_TX_DIAG 0x00 335 336 #define XL_MII_CLK 0x01 337 #define XL_MII_DATA 0x02 338 #define XL_MII_DIR 0x04 339 340 #define XL_MEDIA_SQE 0x0008 341 #define XL_MEDIA_10TP 0x00C0 342 #define XL_MEDIA_LNK 0x0080 343 #define XL_MEDIA_LNKBEAT 0x0800 344 345 #define XL_MEDIASTAT_CRCSTRIP 0x0004 346 #define XL_MEDIASTAT_SQEENB 0x0008 347 #define XL_MEDIASTAT_COLDET 0x0010 348 #define XL_MEDIASTAT_CARRIER 0x0020 349 #define XL_MEDIASTAT_JABGUARD 0x0040 350 #define XL_MEDIASTAT_LINKBEAT 0x0080 351 #define XL_MEDIASTAT_JABDETECT 0x0200 352 #define XL_MEDIASTAT_POLREVERS 0x0400 353 #define XL_MEDIASTAT_LINKDETECT 0x0800 354 #define XL_MEDIASTAT_TXINPROG 0x1000 355 #define XL_MEDIASTAT_DCENB 0x4000 356 #define XL_MEDIASTAT_AUIDIS 0x8000 357 358 #define XL_NETDIAG_TEST_LOWVOLT 0x0001 359 #define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 360 #define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 361 #define XL_NETDIAG_STATS_ENABLED 0x0080 362 #define XL_NETDIAG_TX_FATALERR 0x0100 363 #define XL_NETDIAG_TRANSMITTING 0x0200 364 #define XL_NETDIAG_RX_ENABLED 0x0400 365 #define XL_NETDIAG_TX_ENABLED 0x0800 366 #define XL_NETDIAG_FIFO_LOOPBACK 0x1000 367 #define XL_NETDIAG_MAC_LOOPBACK 0x2000 368 #define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 369 #define XL_NETDIAG_EXTERNAL_LOOP 0x8000 370 371 /* 372 * Window 5 373 */ 374 #define XL_W5_STAT_ENB 0x0C 375 #define XL_W5_INTR_ENB 0x0A 376 #define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 377 #define XL_W5_RX_FILTER 0x08 378 #define XL_W5_RX_EARLYTHRESH 0x06 379 #define XL_W5_TX_AVAILTHRESH 0x02 380 #define XL_W5_TX_STARTTHRESH 0x00 381 382 /* 383 * RX filter bits 384 */ 385 #define XL_RXFILTER_INDIVIDUAL 0x01 386 #define XL_RXFILTER_ALLMULTI 0x02 387 #define XL_RXFILTER_BROADCAST 0x04 388 #define XL_RXFILTER_ALLFRAMES 0x08 389 #define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 390 391 /* 392 * Window 6 (stats) 393 */ 394 #define XL_W6_TX_BYTES_OK 0x0C 395 #define XL_W6_RX_BYTES_OK 0x0A 396 #define XL_W6_UPPER_FRAMES_OK 0x09 397 #define XL_W6_DEFERRED 0x08 398 #define XL_W6_RX_OK 0x07 399 #define XL_W6_TX_OK 0x06 400 #define XL_W6_RX_OVERRUN 0x05 401 #define XL_W6_COL_LATE 0x04 402 #define XL_W6_COL_SINGLE 0x03 403 #define XL_W6_COL_MULTIPLE 0x02 404 #define XL_W6_SQE_ERRORS 0x01 405 #define XL_W6_CARRIER_LOST 0x00 406 407 /* 408 * Window 7 (bus master control) 409 */ 410 #define XL_W7_BM_ADDR 0x00 411 #define XL_W7_BM_LEN 0x06 412 #define XL_W7_BM_STATUS 0x0B 413 #define XL_W7_BM_TIMEr 0x0A 414 #define XL_W7_BM_PME 0x0C 415 416 #define XL_BM_PME_WAKE 0x0001 417 #define XL_BM_PME_MAGIC 0x0002 418 #define XL_BM_PME_LINKCHG 0x0004 419 #define XL_BM_PME_WAKETIMER 0x0008 420 421 /* 422 * bus master control registers 423 */ 424 #define XL_BM_PKTSTAT 0x20 425 #define XL_BM_DOWNLISTPTR 0x24 426 #define XL_BM_FRAGADDR 0x28 427 #define XL_BM_FRAGLEN 0x2C 428 #define XL_BM_TXFREETHRESH 0x2F 429 #define XL_BM_UPPKTSTAT 0x30 430 #define XL_BM_UPLISTPTR 0x38 431 432 #define XL_LAST_FRAG 0x80000000 433 434 /* 435 * Boomerang/Cyclone TX/RX list structure. 436 * For the TX lists, bits 0 to 12 of the status word indicate 437 * length. 438 * This looks suspiciously like the ThunderLAN, doesn't it. 439 */ 440 struct xl_frag { 441 u_int32_t xl_addr; /* 63 addr/len pairs */ 442 u_int32_t xl_len; 443 }; 444 445 struct xl_list { 446 u_int32_t xl_next; /* final entry has 0 nextptr */ 447 u_int32_t xl_status; 448 struct xl_frag xl_frag[63]; 449 }; 450 451 struct xl_list_onefrag { 452 u_int32_t xl_next; /* final entry has 0 nextptr */ 453 u_int32_t xl_status; 454 struct xl_frag xl_frag; 455 }; 456 457 #define XL_MAXFRAGS 63 458 #define XL_RX_LIST_CNT 32 459 #define XL_TX_LIST_CNT 32 460 #define XL_MIN_FRAMELEN 60 461 #define XL_INC(x, y) (x) = (x + 1) % (y) 462 463 struct xl_list_data { 464 struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 465 struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 466 unsigned char xl_pad[XL_MIN_FRAMELEN]; 467 }; 468 469 struct xl_chain { 470 struct xl_list *xl_ptr; 471 struct mbuf *xl_mbuf; 472 struct xl_chain *xl_next; 473 struct xl_chain *xl_prev; 474 u_int32_t xl_phys; 475 bus_dmamap_t map; 476 }; 477 478 struct xl_chain_onefrag { 479 struct xl_list_onefrag *xl_ptr; 480 struct mbuf *xl_mbuf; 481 struct xl_chain_onefrag *xl_next; 482 bus_dmamap_t map; 483 }; 484 485 struct xl_chain_data { 486 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 487 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 488 489 struct xl_chain_onefrag *xl_rx_cons; 490 struct xl_chain_onefrag *xl_rx_prod; 491 struct if_rxring xl_rx_ring; 492 493 /* 3c90x "boomerang" queuing stuff */ 494 struct xl_chain *xl_tx_head; 495 struct xl_chain *xl_tx_tail; 496 struct xl_chain *xl_tx_free; 497 498 /* 3c90xB "cyclone/hurricane/tornado" stuff */ 499 int xl_tx_prod; 500 int xl_tx_cons; 501 int xl_tx_cnt; 502 }; 503 504 #define XL_RXSTAT_LENMASK 0x00001FFF 505 #define XL_RXSTAT_UP_ERROR 0x00004000 506 #define XL_RXSTAT_UP_CMPLT 0x00008000 507 #define XL_RXSTAT_UP_OVERRUN 0x00010000 508 #define XL_RXSTAT_RUNT 0x00020000 509 #define XL_RXSTAT_ALIGN 0x00040000 510 #define XL_RXSTAT_CRC 0x00080000 511 #define XL_RXSTAT_OVERSIZE 0x00100000 512 #define XL_RXSTAT_DRIBBLE 0x00800000 513 #define XL_RXSTAT_UP_OFLOW 0x01000000 514 #define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 515 #define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 516 #define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 517 #define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 518 #define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 519 #define XL_RXSTAT_TCPCKOK 0x40000000 /* 3c905B only */ 520 #define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 521 522 #define XL_TXSTAT_LENMASK 0x00001FFF 523 #define XL_TXSTAT_CRCDIS 0x00002000 524 #define XL_TXSTAT_TX_INTR 0x00008000 525 #define XL_TXSTAT_DL_COMPLETE 0x00010000 526 #define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 527 #define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 528 #define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 529 #define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */ 530 #define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */ 531 #define XL_TXSTAT_DL_INTR 0x80000000 532 533 #define XL_CAPABILITY_BM 0x20 534 535 struct xl_type { 536 u_int16_t xl_vid; 537 u_int16_t xl_did; 538 char *xl_name; 539 }; 540 541 struct xl_mii_frame { 542 u_int8_t mii_stdelim; 543 u_int8_t mii_opcode; 544 u_int8_t mii_phyaddr; 545 u_int8_t mii_regaddr; 546 u_int8_t mii_turnaround; 547 u_int16_t mii_data; 548 }; 549 550 /* 551 * MII constants 552 */ 553 #define XL_MII_STARTDELIM 0x01 554 #define XL_MII_READOP 0x02 555 #define XL_MII_WRITEOP 0x01 556 #define XL_MII_TURNAROUND 0x02 557 558 /* 559 * The 3C905B adapters implement a few features that we want to 560 * take advantage of, namely the multicast hash filter. With older 561 * chips, you only have the option of turning on reception of all 562 * multicast frames, which is kind of lame. 563 * 564 * We also use this to decide on a transmit strategy. For the 3c90xB 565 * cards, we can use polled descriptor mode, which reduces CPU overhead. 566 */ 567 #define XL_TYPE_905B 1 568 #define XL_TYPE_90X 2 569 570 #define XL_FLAG_FUNCREG 0x0001 571 #define XL_FLAG_PHYOK 0x0002 572 #define XL_FLAG_EEPROM_OFFSET_30 0x0004 573 #define XL_FLAG_WEIRDRESET 0x0008 574 #define XL_FLAG_8BITROM 0x0010 575 #define XL_FLAG_INVERT_LED_PWR 0x0020 576 #define XL_FLAG_INVERT_MII_PWR 0x0040 577 #define XL_FLAG_NO_XCVR_PWR 0x0080 578 #define XL_FLAG_USE_MMIO 0x0100 579 #define XL_FLAG_NO_MMIO 0x0200 580 #define XL_FLAG_WOL 0x0400 581 582 #define XL_NO_XCVR_PWR_MAGICBITS 0x0900 583 584 struct xl_softc { 585 struct device sc_dev; /* generic device structure */ 586 void * xl_intrhand; /* interrupt handler cookie */ 587 struct timeout xl_stsup_tmo; /* stats update timeout */ 588 struct arpcom sc_arpcom; /* interface info */ 589 struct ifmedia ifmedia; /* media info */ 590 mii_data_t sc_mii; /* mii bus */ 591 bus_space_handle_t xl_bhandle; 592 bus_space_tag_t xl_btag; 593 bus_space_handle_t xl_funch; 594 bus_space_tag_t xl_funct; 595 struct xl_type *xl_info; /* 3Com adapter info */ 596 u_int8_t xl_hasmii; /* whether we have mii or not */ 597 u_int8_t xl_type; 598 u_int32_t xl_xcvr; 599 u_int16_t xl_media; 600 u_int16_t xl_caps; 601 u_int8_t xl_stats_no_timeout; 602 u_int16_t xl_tx_thresh; 603 struct xl_list_data *xl_ldata; 604 struct xl_chain_data xl_cdata; 605 int xl_flags; 606 void (*intr_ack)(struct xl_softc *); 607 bus_dma_tag_t sc_dmat; 608 bus_dmamap_t sc_listmap; 609 bus_dma_segment_t sc_listseg[1]; 610 int sc_listnseg; 611 caddr_t sc_listkva; 612 bus_dmamap_t sc_rx_sparemap; 613 bus_dmamap_t sc_tx_sparemap; 614 void (*wol_power)(void *); 615 void *wol_power_arg; 616 }; 617 618 #define xl_rx_goodframes(x) \ 619 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 620 621 #define xl_tx_goodframes(x) \ 622 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 623 624 struct xl_stats { 625 u_int8_t xl_carrier_lost; 626 u_int8_t xl_sqe_errs; 627 u_int8_t xl_tx_multi_collision; 628 u_int8_t xl_tx_single_collision; 629 u_int8_t xl_tx_late_collision; 630 u_int8_t xl_rx_overrun; 631 u_int8_t xl_tx_frames_ok; 632 u_int8_t xl_rx_frames_ok; 633 u_int8_t xl_tx_deferred; 634 u_int8_t xl_upper_frames_ok; 635 u_int16_t xl_rx_bytes_ok; 636 u_int16_t xl_tx_bytes_ok; 637 u_int16_t status; 638 }; 639 640 /* 641 * register space access macros 642 */ 643 #define CSR_WRITE_4(sc, reg, val) \ 644 bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 645 #define CSR_WRITE_2(sc, reg, val) \ 646 bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 647 #define CSR_WRITE_1(sc, reg, val) \ 648 bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 649 650 #define CSR_READ_4(sc, reg) \ 651 bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 652 #define CSR_READ_2(sc, reg) \ 653 bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 654 #define CSR_READ_1(sc, reg) \ 655 bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 656 657 #define XL_SEL_WIN(x) \ 658 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 659 #define XL_TIMEOUT 2000 660 661 /* 662 * General constants that are fun to know. 663 * 664 * 3Com PCI vendor ID 665 */ 666 #define TC_VENDORID 0x10B7 667 668 /* 669 * 3Com PCI chip device IDs. 670 */ 671 #define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500 672 #define TC_DEVICEID_HURRICANE_555 0x5055 673 #define TC_DEVICEID_HURRICANE_575A 0x5057 674 #define TC_DEVICEID_HURRICANE_575B 0x5157 675 #define TC_DEVICEID_HURRICANE_575C 0x5257 676 #define TC_DEVICEID_HURRICANE_656 0x6560 677 #define TC_DEVICEID_HURRICANE_656B 0x6562 678 #define TC_DEVICEID_TORNADO_656C 0x6564 679 #define TC_DEVICEID_HURRICANE_556 0x6055 680 #define TC_DEVICEID_HURRICANE_556B 0x6056 681 #define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 682 #define TC_DEVICEID_BOOMERANG_10BT 0x9000 683 #define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 684 #define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 685 #define TC_DEVICEID_BOOMERANG_100BT4 0x9051 686 #define TC_DEVICEID_KRAKATOA_10BT 0x9004 687 #define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 688 #define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 689 #define TC_DEVICEID_CYCLONE_10FL 0x900A 690 #define TC_DEVICEID_HURRICANE_10_100BT 0x9055 691 #define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 692 #define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 693 #define TC_DEVICEID_CYCLONE_10_100FX 0x905A 694 #define TC_DEVICEID_TORNADO_10_100BT 0x9200 695 #define TC_DEVICEID_TORNADO_10_100BT_920B 0x9201 696 #define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 697 #define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805 698 699 /* 700 * 3Com CardBus chip device IDs. 701 * 702 * The third character of the model number indicates either a dongle ('C') 703 * or X-Jack ('X') connector. Presumably, "FE" means "Fast Ethernet", and 704 * the 'M' indicates a NIC/modem combo card. 705 */ 706 #define TC_DEVICEID_3C575_CARDBUS 0x5057 707 #define TC_DEVICEID_3CCFE575BT_CARDBUS 0x5157 /* also 3CXFE575BT */ 708 #define TC_DEVICEID_3CCFE575CT_CARDBUS 0x5257 /* also 3CXFE575CT */ 709 #define TC_DEVICEID_3CCFEM656_CARDBUS 0x6560 /* also 3CXFEM656 */ 710 #define TC_DEVICEID_3CCFEM656B_CARDBUS 0x6562 711 #define TC_DEVICEID_3CCFEM656C_CARDBUS 0x6564 /* also 3CXFEM656C */ 712 713 #define XL_CARDBUS_INTR 0x0004 714 #define XL_CARDBUS_INTR_ACK 0x8000 715 716 /* 717 * PCI low memory base and low I/O base register, and 718 * other PCI registers. Note: some are only available on 719 * the 3c905B, in particular those that related to power management. 720 */ 721 722 #define XL_PCI_VENDOR_ID 0x00 723 #define XL_PCI_DEVICE_ID 0x02 724 #define XL_PCI_COMMAND 0x04 725 #define XL_PCI_STATUS 0x06 726 #define XL_PCI_CLASSCODE 0x09 727 #define XL_PCI_LATENCY_TIMER 0x0D 728 #define XL_PCI_HEADER_TYPE 0x0E 729 #define XL_PCI_LOIO 0x10 730 #define XL_PCI_LOMEM 0x14 731 #define XL_PCI_BIOSROM 0x30 732 #define XL_PCI_INTLINE 0x3C 733 #define XL_PCI_INTPIN 0x3D 734 #define XL_PCI_MINGNT 0x3E 735 #define XL_PCI_MINLAT 0x0F 736 #define XL_PCI_RESETOPT 0x48 737 #define XL_PCI_EEPROM_DATA 0x4C 738 739 /* 3c905B-only registers */ 740 #define XL_PCI_CAPID 0xDC /* 8 bits */ 741 #define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 742 #define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 743 #define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 744 745 #define XL_PSTATE_MASK 0x0003 746 #define XL_PSTATE_D0 0x0000 747 #define XL_PSTATE_D1 0x0002 748 #define XL_PSTATE_D2 0x0002 749 #define XL_PSTATE_D3 0x0003 750 #define XL_PME_EN 0x0100 751 #define XL_PME_STATUS 0x8000 752 753 /* Bits in the XL_PCI_PWRMGMTCAP register */ 754 #define XL_PME_CAP_D0 0x0800 755 #define XL_PME_CAP_D1 0x1000 756 #define XL_PME_CAP_D2 0x2000 757 #define XL_PME_CAP_D3_HOT 0x4000 758 #define XL_PME_CAP_D3_COLD 0x8000 759 760 extern int xl_intr(void *); 761 extern void xl_attach(struct xl_softc *); 762 extern int xl_detach(struct xl_softc *); 763 void xl_init(void *); 764 void xl_stop(struct xl_softc *); 765 void xl_reset(struct xl_softc *); 766 int xl_activate(struct device *, int); 767