Searched refs:adjusted_pix_clk_100hz (Results 1 – 3 of 3) sorted by relevance
206 pll_settings->adjusted_pix_clk_100hz, in calc_fb_divider_checking_tolerance()225 pll_settings->adjusted_pix_clk_100hz) in calc_fb_divider_checking_tolerance()227 pll_settings->adjusted_pix_clk_100hz in calc_fb_divider_checking_tolerance()228 : pll_settings->adjusted_pix_clk_100hz - in calc_fb_divider_checking_tolerance()299 if (pll_settings->adjusted_pix_clk_100hz == 0) { in calculate_pixel_clock_pll_dividers()314 pll_settings->adjusted_pix_clk_100hz; in calculate_pixel_clock_pll_dividers()316 pll_settings->adjusted_pix_clk_100hz) < in calculate_pixel_clock_pll_dividers()325 pll_settings->adjusted_pix_clk_100hz; in calculate_pixel_clock_pll_dividers()447 pll_settings->adjusted_pix_clk_100hz = in pll_adjust_pix_clk()495 pll_settings->adjusted_pix_clk_100hz / 10); in dce110_get_pix_clk_dividers_helper()[all …]
618 int adjusted_pix_clk_100hz) in dcn10_link_encoder_validate_hdmi_output() argument625 adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) in dcn10_link_encoder_validate_hdmi_output()633 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) in dcn10_link_encoder_validate_hdmi_output()636 if ((adjusted_pix_clk_100hz == 0) || in dcn10_link_encoder_validate_hdmi_output()637 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) in dcn10_link_encoder_validate_hdmi_output()647 adjusted_pix_clk_100hz >= 3000000) in dcn10_link_encoder_validate_hdmi_output()
108 uint32_t adjusted_pix_clk_100hz; member